The solar cell industry has been truly remarkable to observe over the past ten years. During this time, the industry has sustained a CAGR of more than 40 percent in cell production. Silicon consumption is currently twice that of the much more mature semiconductor industry.¹ Up until the first half of 2008, attractive operating margins were sustained throughout most of the supply chain. However, since the second half of 2008, like most other industries, the Photovoltaic (PV) industry is experiencing significant challenges. The current credit crisis has impacted initiation of new PV projects and module supply is currently exceeding that of demand. New manufacturing capacity, which was being added to meet the growth frenzy during the first half of 2008, is making a bad situation worse. Companies that entered into long term silicon contracts at the peak of last year are scrambling to renegotiate their contracts to more accurately reflect the significant drop in silicon prices. Some sources are predicting module prices will decrease from $3.80/watt to between $2.50 and $3.00/watt during 2009.²

Enlarge this picture Fig 2 Overview of Wet Chemistry Processing Steps Used in c-Si Solar Cell Manufacturing

Despite these troubled times, the PV industry remains one of the few industries with sustainable long-term growth opportunity. Macroeconomic drivers such as concerns over imported oil dependence and global warming remain strong even during the current economic situation. Oil prices appear to have hit bottom and will likely increase again as the world economy recovers. Although some countries like Spain are reducing government subsidies, other countries like the United States, Japan, and South Korea are showing indications of increasing incentives to create future demand for solar energy. The anticipated sharp drop in the $/watt is a necessary and positive step for the industry to achieve grid parity, which will make solar generated power competitive with power received from the grid independent of government subsidies. As a result, those companies that have managed the growth wisely over the past years should be able to weather the storm and are likely to emerge even stronger than before.

Enlarge this picture Fig 3 Comparisons of Time to Remove Graphite from Silicon Surface. All Chemistries Shown Were Processed at 50ºC

One of the key factors for any solar cell manufacturer to survive during such difficult times is the ability to achieve high device performance at a low cost. Wet chemical processing has been adopted from other more mature industries such as the semiconductor and printed circuit board industries and plays a key role in solar cell manufacturing. The purpose of this article is to highlight the areas where wet chemical processing is being utilized in the solar cell manufacturing process while giving some insight of how it can further improve cell efficiency and overall costs.

Overview

Enlarge this picture Fig 4 Various Wafer Appearances Before and After Clean

Simplistically stated, a solar cell is a semiconductor device that creates electricity from the sun by utilizing the photovoltaic effect (see Figure 1). Photons are absorbed from the sun by the silicon layer and excite nearby electrons sufficiently enough to create a current in an electrical circuit. The most common metric to quantify performance is cell efficiency, which represents the ability of the solar cell to convert sunlight into electricity. An increase in cell efficiency yields more power per device. Depending upon the technology, cell efficiencies can range anywhere from 8 percent to as much as 22 percent in production settings.

Enlarge this picture Table 1

Figure 2 shows a generic process flow for the manufacture of a silicon solar cell. The key steps that currently utilize wet chemistry processing include: post-wafering cleaning, texturing, edge isolation, phosphor silicate glass (PSG) remove/clean, and plated metallization. Table 2 outlines some of the main market drivers for each of these process steps. Depending upon the process line configuration, production throughput for any one of these steps can be in the range of 1500-2800 wafers per hour. Wafers can be loaded into cassettes for batch/vertical processing or loaded onto a conveyor belt for continuous/horizontal processing. Both equipment configurations are currently commercially available on the market from a number of vendors.

Enlarge this picture Table

Wafer cleaning

Enlarge this picture Fig 5 Metal Ion Contamination as a Function of Different Cleaning Chemistries

Most silicon used for the solar cell industry is grown and/or machined to produce blocks called ingots. Due to the different growth processes used, multi-crystalline ingots are square, while mono-crystalline ingots are square with rounded corners. They are typically about 0.54 m. long and have x-y dimensions of 15.6cm x 15.6cm. The wafering process is accomplished by use of a wire saw, which is comprised of a series of very thin stainless steel wires (0.12-0.15mm in diameter) that are wound on two spools. Glycol, oil, or water based lubricants dispersed with silicon carbide abrasives provide the primary cutting action as the wire passes through the ingot. Typical wafer thickness after sawing is about 180-200µm, although thinner wafers have been demonstrated.

Enlarge this picture Fig 6 Pyramid Formation as a Function of KOH Concentration. All Conditions Were Etched for 10 minutes @ 90ºC

After the wafering step, the sliced ingot is placed into a spray chamber to remove the bulk of the silicon carbide slurry. The sliced ingot is then placed in a dip tank with a solvent that can loosen the adhesive (typically an organic acid) and releases the wafers from the mounting plate. Wafers are then loaded into cassettes for vertical/batch mode cleaning or arranged on a conveyor belt for horizontal/continuous processing.

A successful cleaning process, regardless of whether it is in the vertical or horizontal configuration, should have the following attributes:

Fig 7 Resulting Wafer Topography After Acidic Texturing Step on Multi Crystalline Wafer

1. Ability to produce wafers visually free of any lubricant, abrasive, or metal ion residues

2. Ability to work on mono-crystalline and multi-crystalline wafers

3. Wide process latitudes to handle significant variation of incoming wafer cleanliness quality

4. Provide a uniform surface compatible with subsequent texturing/saw damage removal

5. Meet demanding waste stream regulations

Many types of chemistries are used for the cleaning process and include water, surfactants, solvents, acids, and alkalis. However, not all materials clean with the same degree of effectiveness. Figure 3 shows a comparison of how long it takes to clean off pencil lead from a silicon substrate using three different alternatives. It is also quite common to see varying degrees of contamination on the wafers prior to cleaning. Contamination can range from excessive dried SiC slurry to residual metal and metal oxides from the wire during wafering. Contamination from metal oxides can be enhanced visually if they are not removed prior to any silicon etching/removal. Figure 4 shows wafers with different contamination levels pre- and post-cleaning. As a result, it’s important to understand the origin of the incoming wafer contamination so that the proper cleaning process can be optimized to produce a uniform appearance.

As advanced solar cell designs emerge, more cell producers are concerned about residual metal contamination. As a result, wafers need to emerge from the cleaning process with very low trace metal contaminant levels. Figure 5 shows typical metal levels through various parts of the cleaning process.

1. Ability to produce wafers visually free of any lubricant, abrasive, or metal ion residues

2. Ability to work on mono-crystalline and multi-crystalline wafers

3. Wide process latitudes to handle significant variation of incoming wafer cleanliness quality

4. Provide a uniform surface compatible with subsequent texturing/saw damage removal

5. Meet demanding waste stream regulations

Enlarge this picture Fig 8 Examples of Front and Rear Side Metallization on Two Types of Wafers Used in PV Industry

Many types of chemistries are used for the cleaning process and include water, surfactants, solvents, acids, and alkalis. However, not all materials clean with the same degree of effectiveness. Figure 3 shows a comparison of how long it takes to clean off pencil lead from a silicon substrate using three different alternatives. It is also quite common to see varying degrees of contamination on the wafers prior to cleaning. Contamination can range from excessive dried SiC slurry to residual metal and metal oxides from the wire during wafering. Contamination from metal oxides can be enhanced visually if they are not removed prior to any silicon etching/removal. Figure 4 shows wafers with different contamination levels pre- and post-cleaning. As a result, it’s important to understand the origin of the incoming wafer contamination so that the proper cleaning process can be optimized to produce a uniform appearance.

As advanced solar cell designs emerge, more cell producers are concerned about residual metal contamination. As a result, wafers need to emerge from the cleaning process with very low trace metal contaminant levels. Figure 5 shows typical metal levels through various parts of the cleaning process.

Texturing

Enlarge this picture Fig 9 Schematic of Basic Operating Theory for Light Induced Plating

The next step after cleaning is wafer texturing. The texturing step has two primary purposes:

1. Etch the wafer to remove any residual saw damage

2. Provide a matte surface to minimize light reflection

For mono-crystalline wafers, a blend of potassium hydroxide (KOH) and isopropanol (IPA) are typically used to achieve the purposes described above.4 Concentrations of each component can vary depending upon the process but are typically less than 10 percent for each. Process temperatures are between 80oC to 90oC. The KOH provides the anisotropic etching along the <100> plane of the silicon crystal, which exposes the <111> plane. The role of the IPA is to help control KOH etch rate (~1-2 µm/min) and selectivity to the <111> crystal plane, which leads to the random pyramid structure as shown in Figure 6. Balancing the etch rate with pyramid formation is important to ensure that enough silicon is removed to optimize saw damage removal (typically >6µm per side), while maintaining the correct peak density to minimize reflection. Figure 6 also shows how the substrate can be polished etched if the KOH concentration is not kept within the desired range.

Due to the volatility of the IPA, alkaline texturing is typically conducted in vertically configured wet chemical equipment to allow for lower processing temperatures (typically 80oC) while accommodating longer process times (typically 20-30 minutes). However, novel processes are being developed, which can replace the IPA and will enable higher operational temperatures and shorter process times. Such systems also are compatible with inline horizontal equipment configurations.

To achieve uniform texturing across a multi-crystalline wafer, an etching solution that provides an isotropic etch to the different silicon crystal orientations must be used. Typically a blend of nitric acid (HNO3) and hydrofluoric acids (HF) are used to texturize multi-crystalline wafers. The role of the nitric acid is to oxidize the silicon while the hydrofluoric acid is responsible for the bulk etching. Silicon etch rates for acidic texturing are usually in the range of 2-4 µm/min. Due to the exothermic nature of this reaction, process temperatures are typically < 10oC range. Figure 7 shows the resulting topography of a multi-crystalline wafer after being texturized with HNO3/HF process.

Equipment configuration with the acidic texturing process is typically in the horizontal mode. Volatile organic species are less of a concern, but generation of nitrogen oxide gases and safe handling of the acids (especially the hydrofluoric) needs to be considered carefully. Alternative wet chemistries that can minimize or even replace the use of hydrofluoric acid are currently being researched.

For either alkaline or acidic processes, a final hydrochloric rinse step is used to remove any metal ion contamination prior to the p-n junction formation step.

Doping/PSG etch/edge isolation

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The next step in the manufacturing process is to create the p-n junction through a doping step. Dopant chemistry is deposited and diffused into the solar cell to create a thin layer called an emitter layer. Most of today’s crystalline silicon solar cells start off as a p-type doped wafer and the emitter layer is n-type doped. The most common n-type source is phosphorous, which can be applied using chemical vapor deposition or by use of spray/mist application. Phosphoric acid based solutions are used as the doping source for spray applications. The wafers are then fired to peak temperatures of over 850oC to diffuse the phosphorus into the silicon. The resistance of the emitter layer can be adjusted by varying the amount of material sprayed onto the wafers and/or by changing the firing temperature/time.

During the diffusion step, a phosphor silicate glass (PSG) is formed on the surface and must be removed. Typically this step is achieved using a glass etch step, which is comprised of a dilute hydrofluoric acid solution.⁵ Unlike the texturing step, the PSG etch step does not contain any oxidizers so that the selectivity of the HF to the underlying emitter layer is quite good. Subsequent cleaning of the wafers surface may be followed to ensure the surface is completely removed of any residual PSG.

The emitter layer is now present on both sides (and/or on edges) of the wafer and must be isolated to prevent short circuiting the solar cell. Edge isolation can be accomplished using laser ablation, plasma etching, or wet chemical etching. Wet chemistry isolation is accomplished by immersing the rear side and edges of the wafer in an HF-based chemistry. Due to surface tension effects between the substrate and chemistry, the emitter layer on the front side is not exposed to the etchant. Wafers are then coated with a thin layer of silicon nitride, which improves device reliability and serves as an anti reflection layer.

Metallization

The purpose of metallization on solar cells includes the following:

1. Provides a means of collecting electrons from the front side of the cell

2. Creates a back surface field that improves the electron migration properties within the bulk silicon

3. Creates a mirror on the backside of the wafer to reflect light back into the wafer

4. Provides a means for connecting numerous cells to create a working module

Figure 8 shows some examples of multi-crystalline and mono-crystalline silicon solar cells that have been metallized on the front side and rear side, respectively. Traditionally, the front side grid (FSG) metallization is accomplished by using fritted silver pastes while the backside of the wafer is metallized with a combination of silver and aluminum fritted pastes. In order to make contact through the silicon nitride layer to the underlying silicon layer, the pastes are first dried at temperatures around 150oC and then fired at temperatures over 850oC for a few seconds.

Recently, plating of wafers in combination with, and/or in replacement of, screen printed metallization has been getting increased attention. Plating of solar cells can be done with electro-less or electrolytic techniques. For some applications, such as depositing a thin seed layer that is less than 1µm thick, electro-less plating can provide sufficient plating rates to fit into production requirements. Electro-plating is used to build thicker deposits, but making contact to the front side of the wafer can be challenging as the wafers are only 180-200 µm thick and can break easily.

An alternative method called Light Induced Plating (LIP) has been developed that takes advantage of the current generation properties of the solar cells.⁶ As Figure 9 shows, the wafers are placed faced down and travel across a series of lights, which creates a localized electric field on the front side of the wafer. Contact is made on the backside of the wafer with specially designed contact rollers. The voltage of the roller can be controlled to minimize anodic dissolution and attach on the backside of the wafer, thereby creating preferential plating of the desired metal on the front side.

Enlarge this picture Fig 11 Solar Cell Performance Improvement Due to LIP Ag Plating Process

One of the primary improvements wafer plating offers over existing paste technology is through improved deposit conductivity. Figure 10 shows a picture of a silver plated deposit over screen printed silver paste. Note the porosity in the paste deposit as compared to the plated deposit. This porosity decreases the overall conductivity of the deposit, which in turn creates a collection finger that is higher in resistance as compared to a plated feature that is solid. The data in Figure 11 shows the decrease in series resistance and corresponding increase in cell efficiency as a result of the LIP silver plating process (Enlight 620) versus using paste alone.

As with most plating processes, the deposition process is isotropic in nature, which means that the line width is increasing as thickness increases. Although this effect can have a small impact on increasing the degree of shadowing, it also can help to improve yield distributions by mending discontinuous seed layers that result from wetting problems/defects from the screen print process.

New cell designs are emerging that utilize much thinner finger designs to improve the overall electron collection efficiency and to reduce shadowing effects. Unfortunately, screen print technology has limited resolution below 80µm. Recent advancements with inkjet and aerosol deposition technology are allowing for seed layers to be deposited with resolution in the 30-40µm range. Plating is required because these seed layers are typically quite thin and would result in very high resistance values of the final collection finger.

Recent cost pressures have created the demand for lower cost materials that can be used for metallization such as copper. It is well published that copper has the ability to migrate through bulk silicon, which can compromise the p-n junction and ruin cell performance. If copper is to be used for metallization purposes, then a barrier layer such as nickel must be used. It is important to note that the silicon nitride layer should be sufficiently dense enough so as to not expose the underlying silicon layer, which would result in background plating and increased copper migration. Screen print technology is not conducive to depositing nickel or copper deposits and, therefore, most of the attention is being placed on using plating technology to realize copper metallization.

Summary

Despite going through some growing pains, the photovoltaic industry is well positioned to continue growing over the long term. Wet chemical processing technology from the semiconductor and printed circuit board industries have successfully been adopted in most crystalline silicon manufacturing lines. The technology is being used in a number of different process steps with various equipment configurations and process chemistries. In order to meet future demand for improved cell performance at lower costs, continued improvement in the process capabilities will be required. As new processes are introduced, it will be important to consider the impact they may have on subsequent processing steps and overall cell performance.

Acknowledgements

1. Photon International, March 2009, p 88
2. Solar Market: Dip in 2008, Rise by 2011, Retrieved on 4/13/2009 from http://www.redherring.com 3. Photon International, March 2009, p 190 4. Sparber et al, Comparison of Texturing Methods for Monocrystalline Silicon Solar Cells Using KOH and Na2CO³, Conference on Photovoltaic Energy Conversion, 2003
5. Wet Chemical Edge Isolation for Solar Cells, Euro-Asia Magazine, September 2007, Retrieved on 4/12/2009 from http://www.euroasiasemiconductor.com/euroasia-magazine/online-midseptember2007
6. Allardyce et al, The Commercial Application of Light Induced Electroplating for Improving the Efficiency of Crystalline Silicon Solar Cells, 22nd EU PVSEC, Milano, Section 2-2.2