Bannockburn, Ill. — IPC — Association Connecting Electronics Industries® has released the B revision of IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. The leading industry standard for surface mount land pattern design and layout, IPC-7351B provides designers and printed board fabricators with updated guidance on requirements of land pattern geometries used for the surface attachment of electronic components, as well as surface mount design recommendations for achieving the best possible solder joints.

 

"The new IPC-7351B standard introduces several new component families and lead forms that include micro-miniature flat-lead and no-lead components, and a new padstack standard naming convention," says Tom Hausherr, EDA library product manager, Mentor Graphics Corporation and member of the IPC 1-13 Land Pattern Subcommittee. "Overall, the IPC-7351B standard is a key publication in the electronics industry for accurate CAD library generation."

 

A major addition to IPC-7351B, the new padstack naming convention consists of combinations of letters and numbers that represent the shape or dimensions of lands on different layers of printed boards or documentation. The padstack naming convention enables a designer to convey all variations and dimensions of a padstack, employing it in combination with intelligent land pattern conventions also defined within the standard, according to design rules established in the IPC-2220 design series.

 

A popular document that covers land pattern design for all types of passive and active components, IPC-7351 directs users on an appropriate land pattern based on desired component density through the provision of three separate land pattern geometries for each component. The new B revision of the standard introduces land pattern design guidance and rules for new surface mount component families such as electrolytic aluminum capacitors (CAPAE); small outline diode, flat lead (SODFL) and small outline transistor, flat lead (SOTFL); and dual flat no-lead (DFN) devices.

 

Several device families, including DPAK, QFP (quad flat pack) and QFN (quad flat, no-lead), often feature thermal pads on the bottom of the packages that expose the die to the printed board surface, which maximizes the efficient heat transfer path when these devices are soldered to the printed board. The usage of such thermal pads, however, carries a risk of the component floating on top of the solder. Therefore, IPC-7351B now provides a default paste mask for those pads to allow the package body to settle. The B revision of the standard also expands its lead free coverage with the addition of new solder alloys and presents thoughtful discussion on etch-factor compensations at the designer level as well as at printed board fabrication. In addition, IPC-7351 has been edited significantly by users of the standard to enhance its clarity and understanding.

 

A half-day workshop on the updates to IPC-7351 will be held on September 29, 2010, at Electronics Midwest in Rosemont, Ill.

 

For more information, visit www.ipc.org/7351.