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It was in the spring of 2008 in Shanghai, after my talk at the ECWC conference, when I was asked about the differences and similarities of Integrated Circuit (IC) fabrication processes and the processes used in substrate and circuit board fabrication. And a related question tried to probe if fabrication technology for ICs was being adopted by electronic package fabricators, and vice versa.

I answered that, from my perspective, it looks like a two-way street. The first example that came to mind was the introduction of copper electroplating into IC fabrication. Copper electroplating has been used in PWB fabrication ever since double-sided boards and multilayer boards were introduced. Much progress has been made over the years in copper electroplating that now benefits the dual-damascene process by which conductive paths are formed in the redistribution layers of ICs.

Another example is the introduction of the multilayer concept into the world of ICs. Multilayer PWBs are basically a number of signal, power, and ground layers stacked on top of each other and interconnected through-plated through holes, which are formed by drilling, metal seed layer deposition, and copper electroplating. ICs, on the other hand, have only one functional layer in which all semiconductors reside, the equivalent to a single-sided board. With the advent of 3D stacked die we have seen the introduction of what could be called an IC multilayer, featuring TSVs (through silicon vias) that are drilled (etched) and metalized to interconnect the stacked chips. The function of organic bonder material that seals the space between the chips can be compared to that of prepreg layers in multilayer PWBs.

If we look for examples of IC technology that is being adopted into substrate fabrication, Amkor’s Viking process comes to mind. This process, and several others, uses the dual-damascene process concept to form circuits in trenches (recessed circuits) as well as micro-via connections. Laser ablation of the dielectric forms the recessed features. An electroless copper seed layer is deposited and copper is built-up by electroplating, using a plating process that preferentially deposits in recessed areas. Excess surface copper is removed by a planarization step (or a sequence of steps) that is not unlike the CMP (chemical mechanical planarization) practiced in IC fabrication. Other processes that form recessed circuits may use imprint technology or transfer lamination instead of laser ablation.

I ran across another interesting example of blended IC and PWB fabrication when I was reading US patent 7,462,784 (December 9, 2008) awarded to Kariya-san and others of Ibiden. I had met Kariya-san a few years ago when we discussed microvia reliability issues. What is described in US 7,462,784 can be viewed as an advanced flip chip package where the typical BT (bismaleimide triazine) rigid core is replaced with a silicon core. The patent describes a “multilayer printed wiring board” that is analogous to the classic flip chip package that has a rigid BT core with plated through-holes and ABF (from Ajinomoto) build up layers, with microvias, except that the rigid core of the invention is a thin, polished silicon core.

The objectives are to:

• reduce the CTE of the package to about 3 to 10 ppm/K whereby the CTE of the silicon dominates the overall CTE of the package. The objective is to minimize CTE mismatch and stress between the package and the chip, thus avoiding cracks in the build-up dielectric.
• achieve even finer circuitry by building on a very flat surface. Apparently, the surface of a BT core, which is reinforced by a glass weave, is sufficiently uneven to present a problem to very fine photolithography.
• move some of the wiring in the IC, i.e. the low K copper layers, to the top build-up layer circuitry, which allows higher chip yield and lower chip cost.

The fabrication process starts with a polished thin silicon piece. Through-holes are formed by plasma etch (DRIE, deep reactive ion etching), sandblasting, or UV laser drilling. Then the surfaces and through-hole walls are insulated by the formation of SiO2 (either by high temperature oxidation or CVD). Then a metal seed layer is formed on all surfaces either by sputtering or e-less plating. The through-holes are then "plated shut" by copper electroplating. The surface copper is then thinned by CMP and the core is circuitized. Then ABF or polyimide dielectric layers are applied to both sides, microvias are drilled followed by semi-additive processing. There can be more than one build-up layer on each side. Some of the processing steps involve the use of a temporary support carrier. Finally, soldermask is applied and patterned. E-less Ni and Au are deposited before solder bumps are formed.

Other interesting cases are the “all silicon” packages under development, although it is a bit of a stretch to cite these developments as an example of applying IC technology to organic packages since the organic has given way to an all silicon solution.