CircuiTree Asian SectionCircuiTree
  Home
  Subscribe
  eNewsletter
  Online
  Breaking News
  Blog
  Bulletin Board
  Podcasts
  Videos
  Web Exclusives
  Product Showcase
  Showrooms
  Webinars
  Current Issue
  Cover Story
  Features
  Columns
  Calendar of Events
  Resources
  Archives
  Classifieds
  Career Center
  Digital Edition Archives
  Buyers Guide
  Industry Links
  Market Research
  CT Info
  Special Collections
  The Board Authority
  20th Anniversary Perspectives
Search in: EditorialProductsCompanies
New Final Finish Candidate for IC Packages
by Dennis K. W. Yee
January 1, 2007

ARTICLE TOOLS
EmailEmailPrintPrintReprintsReprintsshareShareshare Use

Figure 1. Cutaway view of SiP-PBGA showing die and passive components mounted to the PBGA substrate (Amkor).
Figure 1. Cutaway view of SiP-PBGA showing die and passive components mounted to the PBGA substrate (Amkor).


The rapid growing demand for handheld devices, such as cell phones, personal digital assistants, camcorders, etc., pushes technology to produce smaller, faster, lighter, and more functional devices. It increases the number of features without changing, or even reducing, the device sizes. On IC packaging, the use of system-in-package (SiP) is increasing to fulfill the technology and market needs. It is characterized by any combination of more than one active electronic component of different functionality, plus optionally passives and other devices like microelectromechanical systems (MEMS) or optical components assembled, preferably, into a single standard package that provides multiple functions associated with a system or sub-system.

It may be required to apply wire bonding, flip chip, and surface-mount processes on a substrate. This change impacts the substrate of the IC package--to provide a platform for the assembly of different kinds of components using different assembly techniques.


Use of Nickel-Palladium-Gold Finishing

Palladium plating film has good gold wire bondability and solderability. It has been used and proven on IC lead frames for years. The typical plating thickness of palladium and gold is 0.1 – 0.15 micron and 0.005 micron respectively. The first purpose for applying palladium plating to lead frames was to reduce package assembly time by omitting the multiple plating processes of solder plating on the outer-lead and silver plating on the bonding area at the package process. Now, it has also been recognized for fulfilling the lead free requirement of the RoHS directive.

The electroless nickel, electroless palladium, and immersion gold (ENEPIG) process is a suitable candidate for the IC package PCB substrates--especially for SiP products. As electrolytic nickel palladium gold plating, ENEPIG is also good for both soldering and wire bonding. A layer of 0.2 micron electroless palladium and 0.03 micron immersion gold on electroless nickel could provide wire bonding and soldering capabilities. Unlike the electrolytic process, the ENEPIG process does not need bussing lines, which provide extra flexibility on the circuitry design and enable high-density design for current advanced products and future needs.

Unlike the electroless nickel immersion gold (ENIG) process, ENEPIG does not have a “black pad” issue. The palladium is plated on the electroless nickel by chemical reduction instead of displacement reaction, therefore there is no attack on the electroless nickel layer.


Enlarge this picture
Figure 2. Auger analysis of the plating interface of ENIG (left) and ENEPIG (right).
Figure 2. Auger analysis of the plating interface of ENIG (left) and ENEPIG (right).
By Auger analysis (Figure 2), it is proven that there is a phosphorus rich layer between the nickel and palladium layer and also no phosphorus rich layer between palladium and gold. There is no “corrosion” of the nickel layer by the palladium plating process and also no excessive corrosion of the palladium layer by the immersion gold plating process--because of the low phosphorus content of the electroless palladium layer (~3%P) and low thickness of immersion gold.


Figure 3. SEM analysis of the ENEPIG surface before (left) and after (right) gold stripping.
Figure 3. SEM analysis of the ENEPIG surface before (left) and after (right) gold stripping.
Using scanning electron microscope (Figure 3), it is clearly shown that there is no hyper-corrosion observed on the electroless nickel surface and grain boundaries. Functionally, ENEPIG has solderability and bondability similar to ENIG and electrolytic plated nickel gold, respectively.

On material cost, the ENEPIG process is cheaper than either electrolytic bondable gold or electroless bondable gold process--assuming the gold metal and palladium metal prices are $18/g and $9.6/g, respectively. Since the density of gold (19g/cm3) is about two times that of palladium (10g/cm3), with the same plating thickness, the metal cost of palladium is only about one forth of the metal cost of gold. There is up to an 80% savings on the final finishing processing cost by using ENEPIG instead of electrolytic nickel gold process. The typical saving is about $5/sq.ft. board area.


Technical Concerns

Enlarge this picture
Figure 4. Soldering results &#8211; As received and after aging to 1,000h at 150<sup>o</sup>C.
Figure 4. Soldering results – As received and after aging to 1,000h at 150oC.
Assembly Parameters Re-Optimization

For both wire bonding and soldering, parameters re-optimization might be required for the best results.

Ternary (Cu,Ni)6Sn5 IMC Problem

There is concern on the use of nickel for lead-free solder. The bulk SnAgCu lead-free solder microstructure as reflowed is comprised of a dispersed eutectic phase which consists of small Ag3Sn and Ni3Sn4 particles in a tin matrix. During soldering, palladium and gold rapidly dissolve into the melted solder, which causes the nickel underlay to contact the solder and forms intermetallic compounds. Nickel from the pad, together with tin and copper, form the solder participate in the reaction to form a ternary intermetallic (Cu,Ni)6Sn5 at the interface, which is observed on top of the Ni3Sn4 (formed on a nickel surface). There is high dislocation density from differences in crystal structure and lattice (between Ni3Sn4 and (Cu,Ni)6Sn5). Voids will grow at the Ni3Sn4/(Cu,Ni)6Sn5 interface and increase the probability of failure. However, for IC packaging applications, as the solder joints are fixed by the underfill, this potential risk is minimized or eliminated.


Conclusion

Enlarge this picture
Figure 5. ENEPIG with SnAgCu, 10 times reflowed, 500 thermal cycles.
Figure 5. ENEPIG with SnAgCu, 10 times reflowed, 500 thermal cycles.
ENEPIG is a universal finish for both soldering and wire bonding applications. It is also a potential final finish candidate for next-generation and advanced IC packages.


This article was presented at the TPCA Conference 2006 and is reprinted with TPCA’s permission.


Dennis K. W. Yee
Research, Development and Engineering Manager, Rohm and Haas Electronic Materials


Did you enjoy this article? Click here to subscribe to the magazine.
Buyers Guide
Buyers Guide Comprehensive PWB services and suppliers team directory to find the suppliers and distributors you need fast.

CT University Webinars
Dairy 100 CircuiTree University Webinars are your easy, effective and convenient way to get educated and informed on the latest industry trends and topics.

eNews

eNewsletter Up-to-the-minute information on the latest industry news.

Subscribe Now!Subscribe to Circuitree
Circuitree is the only global magazine to focus on the printed circuit board! Monthly editorials exclusively provide info for circuit board fabricators, suppliers and OEM customers. Subscribe Today!
Subscribe








BNP Media