PCB manufacturing grows more and more complex, seemingly with each day. It involves critical steps and requires detailed parameters about PCBs being manufactured so that they can be efficiently built and will function correctly. This article focuses on key methods and technologies to effectively prepare and hand off the PCB design to manufacturing. Figure 1 illustrates an effective design and handoff process to manufacturing.

As a PCB design is nearing completion and is being readied for initial PCB manufacture, there is typically interface between the designers and the manufacturing engineers. This process is generally known as new product introduction (NPI). The design is analyzed for overall manufacturability and prototypes are generally built to ensure success when the product is switched to volume production.

For NPI, fast turnaround and quick results are preferred versus maximizing production volumes. Test strategies usually involve a flying probe test and bench-top boundary scan, as opposed to in-circuit test with an embedded boundary scan. Assembly equipment is typically set up for smaller match for multiple products to be produced with minimal setup changes.

Preparation of Data Is Critical

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PCB manufacturing requires knowledge about the components and where they are positioned and fitted on the board, plus the electrical connectivity between these components. Data primarily comes from two sources: the physical makeup of the PCB provided by intelligent ECAD layout files or unintelligent Gerber files and the component list or bill of materials (BOM) file for the remaining data. While these sources provide a lot of the data, more information needs to be manually added to provide a complete data set necessary to run manufacturing.

The design environment usually has BOM files and variant data, defining part substitution or omission for multiple products on one PCB design, which can be used by manufacturing. This data should be considered as the design BOM and does not necessarily represent the same information that will be used to construct production boards.

Global board manufacturing companies typically source components locally. These components are electrically compatible with the design, but they may be slightly different physically to the actual part specified by the designer. This introduces another source of data: the approved vendor list, providing data on approved parts that can be used instead of the originally specified part.

BOM Data

BOM data is probably the area that encounters the most variation for input data within manufacturing. This data can be supplied to manufacturing in binary or ASCII formats; can be structured or unstructured; and available as text, HTML, PDF, Excel, or just a piece of paper.

Available tools for parsing BOM files and transforming them into structured, intelligent information can be used in manufacturing, and the data typically consist of part numbers, value, tolerance, description, and package fields. Also, the BOM lists components that will actually be placed on the final board variation so, by inference—those parts not listed in the BOM are components that won’t be placed. These parts are described as no pops or not fitted components and are equally important as PCB manufacturers may want to specifically check that they have not been placed.

Schematic Data

The main PCB data that drives manufacturing is generated from the design layout tools; however, this data does not contain all the information that is available in the design environment. Much of the electrical information can be found in the schematic capture tools, but this data is not passed on to the layout tools; thus, some information fails to get to manufacturing in a usable format. Today, schematic data is provided as a printed circuit diagram that can be hundreds of pages long—virtually impossible to navigate—or, at best, a searchable PDF file that must be manually mined for additional data. Providing complete, intelligent schematic data to the manufacturing environment significantly improves time to market goals. This electrical information is ultimately merged together manually by manufacturing, but it needs to be provided in a useable format capable of accelerating manufacturing—not hindering it.

Design for Manufacturing Analysis

There are a number of checks and verification methodologies to ensure efficient, error-free PCB manufacture. Design rule checking confirms that the PCB is designed to certain pre-defined criteria. Design for fabrication detects and corrects PCB fabrication issues that could affect the performance of the final board. There are also manufacturing-specific checks that are performed to highlight possible issues that are process-dependent; this is called design for manufacturing, or DFM.

For example, fiducials (small features on the board that are used for alignment of both the board and individual components) have no affect on the actual performance of the product, but they are used extensively as part of the manufacturing process. Without these features, the automatic placement and inspection equipment would not be able to reliably place or inspect many of the components on the board.

Tooling holes are features used to fasten the board in the final product and in the manufacturing process, but they have different requirements. For example, two minimum size tooling holes used to hold the PCB on the test fixture for electrical test purposes might also be in diagonal corners of the board to reduce alignment issues.

It is very common for substitute parts to be used instead of the original design-specified parts. As a result, manufacturing issues can arise because the relationship of the component pin to the board land pattern may be affected. For instance, the distance from the toe, heel, and sides of the pin to the land pattern can be enough to cause less-than-optimal solder results. Or worse, the component may not even fit on the land pattern at all. These are critical issues that need to be discovered before products are produced in volume.

Design for Test Analysis

Design for test (DFT) analysis covers two areas within manufacturing: electrical DFT and physical DFT. The former can be employed in the design environment but is equally useful in manufacturing. Design requirements may lead to issues that greatly affect the ability to produce the product. For example, in normal operation, an IC might always need to be enabled so a designer may tie the component’s chip enable (CE) directly to a power or ground rail. For normal board operation, this is perfectly acceptable; however, for sufficient testability of this part (or its surrounding parts), the test engineer must be capable of disabling the component at certain times for acceptable test coverage. Adding a simple resistor between the CE pin and the rail with a test point provides the test engineer with access to improved coverage, therefore improving overall production yields and detecting manufacturing issues earlier.

Physical DFT analysis is used to provide initial coverage estimates based on the level of physical access that the test engineer has to the board. Once the design is complete, further analysis is used to implement the test strategy based on the goals of manufacturing. During the NPI process, DFT analysis helps determine the availability and coverage that boundary scan tests could achieve. It can also be used to analyze the board for flying probe tests and to generate programs that can be used to drive the flying probe test systems.

Stencil Creation Process

Once the final land pattern and solder mask layers are created, stencil layers can be created from the paste layers or derived from the land pattern layers. These will be used to create the stencil used to apply solder paste to the appropriate areas of the board in the required quantity. The stencil apertures can be a percentage reduction in the size of the original copper pad, a specific distance inset from the copper pad, or some form of custom aperture that is not related to the copper pad underneath but more a function of the package that will be placed on the land pattern. For example, two-pin surface-mount components usually have an aperture that looks like a baseball home plate but with the points of the aperture pointing inward toward each other.

Centroid Generation

Figure 2 Software That Allows for Correct Part Placement

One of the most frustrating problems in PCB manufacturing can be determining the correct rotation of a part on the board. This may seem a simple task at first, given that the component rotation is specified in the source PCB layout data. However, that rotation is of the geometry of a component relative to the final rotation on the board. Thus, two 1206 SMD components that need to be placed with pin 1 to the east and pin 2 to the west can have two different rotation values depending on how the 1206 land pattern geometry was defined.

To further complicate this area, the component will have a specific feeder rotation in the automatic insertion machine that ultimately places the part. This needs to be factored into the final component rotation that the machine uses so that the part does indeed get placed with the correct orientation.

Some software solutions use a normalization algorithm on the source CAD data that creates a centroid marker for each component placement. This can be positioned and oriented separately from the land pattern rotation. For assembly rotation output files, this centroid marker will be used to create the correct component position and rotation so that the machine can successfully apply the final feeder offsets—thus correctly placing the component on the board. Figure 2 shows one such software solution displaying part placement.

Manufacturing for Volume

Line utilization measures how much time a line is producing boards as a ratio to the time not spent producing boards. In reality, line utilization varies from 20 to 35 percent in most PCB manufacturing lines—in other words, the majority of the time the line is not producing boards due to machine failures, lack of components, or product changeover. Increasing line utilization by single percentage points can have a huge impact on the profitability of a PCB manufacturer.

In volume manufacture, the line is tuned more for higher production volumes but not necessarily for ultimate speed. Some single products are pushed down dedicated production lines 24 hours, every day. In this line, optimization is the key to producing the most boards in a given amount of time. However, it may be desirable to slow a specific line down because different variants of the board need to be produced without significantly changing the configuration of the line.

Repair and Rework Process

Even the most optimized production line will generate defects that cause the final board to not function correctly. The defects need to be accurately detected and repaired. Depending on the configuration of the production line, boards to be manufactured, and the volumes to be produced, the manufacturer may deploy various techniques to detect product defects and correct them.

As test and inspection equipment is used for process control or defect detection, a repair or rework station will usually be deployed in conjunction. If boards fail the test or inspection stage, they are removed from the production line and are passed on to the repair and rework loop. Here the fault ticket produced from the test or inspection equipment will be used with the knowledge of the repair engineer to determine whether the board can be repaired or must be scrapped.

Once the board has been repaired, it will usually be moved back into the production line to be tested or inspected again at the same point it failed. This confirms that the repair actually did resolve the defect reported. In some cases (the level of this varies from technique to technique), the equipment may highlight a board problem that does not exist. These are called false failures and cost the manufacturer money because it means time wasted trying to diagnose an issue that does not exist. It also increases the level of work in progress where the product is stalled within the production line and is not being shipped.

To optimize the defect detection capability and minimize false failures, a PCB manufacturer can deploy different test strategies that fit the board and defect spectrum generated by that specific line.

Applying Test Strategies

If boards were produced correctly, there wouldn’t be a need for test techniques. But the manufacturing process is not perfect. Even the best manufacturers in the world, making thousands of identical products a day, generate defects that cost the company time and money. The challenge is determining how much testing is required and where to apply it.

As a board travels down the production line, more and more components are added to the board, increasing the opportunity for defects. The odds of a defective board being manufactured at the bare board stage may be close to 100 percent, but once it is fully populated with all the components, highly dense boards may be closer to 50 percent. For a manufacturer producing millions of boards per day, this is an unacceptable number of boards being repaired in functional test—even worse, being shipped to the customer. However, it is possible to estimate the defects per board and associated yields at each stage of the production line and to implement test and inspection strategies that integrate with the overall product quality goals.

Tracking Defects Per Board and Yield

Estimating a product’s future process yield is possible using historical defects per million opportunities (DPMO) data for the components specified on the BOM. DPMO is a normalized assessment of the defects generated in the PCB manufacturing process. The estimated PCB defects per board is the sum of all the individual DPMO numbers associated with all of the components fitted to the board divided by 1 million. For example, if there are three components on the board with the following DPMO values—R1 1500, R2 3500, and C1 5000—the total defects per board will be (1500 + 3500 + 5000)/1,000,000 = 0.01. Using the equation Yield = e^{-(defects per board)}, the process yield of building this board can be found. In this case, it will be e-0.01 or 99 percent. Now consider a board with 1,000 components with an average DPMO value of 500. This gives a process yield of 60 percent or, put in other terms, 40 percent of the board produced will be bad. If the board costs USD 10 to produce and 10,000 are manufactured each day, then over a year the bad boards will cost USD 14.4 million. If we could invest USD 2 million in a test strategy that could detect 95 percent of the defects produced, enabling them to be fixed, we would only have 1,800 bad boards at a cost of USD 18,000—a net savings of USD 12.382 million. In this case, we have improved yield from 60 to 99.95 percent. This then has a significant return on investment.

Conclusion

Applying key DFM and test methodologies results in higher productivity gains, shorter time to market targets, and increased overall product quality. These tools and processes, including a formula to determine board defects and yield, should be considered for optimum success.