Signal integrity in the design of backplanes and multi-gigabit serial links has become one of the most vexing problems in high-speed digital design. As aggregate backplane speeds exceeded 1 and 2.5 Gbits/sec in the early 21st century, designers learned that problems in planning for timing skew and trace analysis increased exponentially from slower designs. In recent years, 10 Gbit/sec Ethernet emerged as a common standard in both backplane and serial-link development, with plans for 40 and 100 Gbit follow-ons.

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Developers in both backplane and short-range fiber link designs have relied on physical probes and behavioral simulation to gain a necessarily limited view of signal characteristics. While test equipment companies are making every effort to increase the speed of probes into tens of gigabits per second, testing at speed has become problematic, while behavioral simulation of such high-speed links sacrifices accuracy.

The utility of adding bit-compare circuitry to I/O devices is one means of overcoming incomplete signal information. When a waveform can be accessed after equalization and before digital bit-stream conversion, as a regular hardware element of a clocking or error-correction chip, signal analysis can be performed much easier than in a testbed with a physical probe.

Introduction

Commoditizing high-speed serial links would not have been possible without the advances made in the last decade in high-speed equalization and dispersion compensation. In particular, the embedding of dispersion-compensating equalizers directly into receivers allowed error-free signals to be received from a transmission noisy enough to display an eye diagram that was all but closed. Embedded equalization, however, means a receiver’s output is no longer available for analysis.

Further digitization of the receiver chain and use of nonlinear equalization may all but obsolete the traditional oscilloscope. Without embedded support for signal visibility within receiver chips, developers may be forced to rely on traffic-generation and simulation products from the test community, which provide, at best, a partial analysis of signals based on simulated traffic rather than real-time data.

The move by test equipment manufacturers to develop golden simulation models for receiver front-ends can be attributed, in part, to the declining utility of eye diagrams. Traditionally, the hexagonal region of an eye mask provided the time and amplitude parameters within which acceptable bit-error-rate performance could be expected. But as equalization methods improved at the same time serial speeds approached 10 Gbits/sec and greater, the assumption that recoverable signals required open eyes no longer held. At present, significantly degraded eye diagram displays can still recover acceptable signals. As DSP methods for equalization improve, eye masks indistinguishable from noise still may offer recoverable signals.

Test equipment companies have sought to augment software-only solutions with in situ probes, though high-speed serial links and backplanes have difficult hurdles to overcome. Any type of probe, even a passive device, adds capacitive loading to a system, and an active probe can have direct impact on available bandwidth. An oscilloscope cannot be used in place of the receiver device when traffic is present, as it opens the communication loop.

In an effort not to obsolete their equipment, manufacturers of oscilloscopes have offered many software packages to approximate the post-equalization waveform by emulating the receiver equalization. The continued improvement of simulation models can make such emulation methods useful, but it is important to emphasize that such methods do not view the true signal.

Instead of working against the trends for better on-chip signal processing, we propose a means of taking advantage of trends in VLSI integration, signal processing, and real-time signal analysis. By integrating circuitry on a transceiver chip that allows direct scanning of the data eye, a data stream can be output that is representative of the input waveform. The evolution of such bit-compare architectures has allowed the implantation of the architecture on a per-pin basis. The prototype design is advanced enough to allow for implementation of a real-time architecture that can eliminate the need for probes, while providing full access to signal characteristics within a serial data path.

On-Chip Adaptive Sampling

Luckily, the ability to embed signal analysis within a high-speed communications chip does not require any breakthroughs in design. By applying existing clock and data recovery (CDR) circuits with new sampling methods, specialized circuit blocks can be implemented to sample signals on a per-pin basis. The method uses the same channels for receiving data and scanning data. This not only assures accurate real-time analysis of the signal but carries fringe benefits of reducing overall power dissipation on the receiver chip and reducing overall complexity of the design.

Why locate the scan at the CDR? This is precisely where post-equalization signals transfer from analog to digital domain and is the unique place in the system design where tuning information from CDR and voltage information are both present. As long as the CDR can provide information to a sampling flip-flop, a variety of CDR architectures can be used for a scanning task, allowing the CDR to be tailored to the particular receiver application. The only requirement for the design is that the phase-locked loop at the core of the CDR be able to extract a clock signal with low jitter and high loop bandwidth, while working independently of the clocking function.

Enlarge this picture Figure 2 Dual Sampling Embedded Waveform Viewing Architecture

In one optimal design, the receiver itself is implemented as a programmable variable-gain amplifier. Because the gain of the receiver is programmable, input signal strength can be controlled, improving waveform scanning. Programmability also allows better control of peak-to-peak voltages, preventing clipping of the p-p voltage swing.

If the variable voltage threshold is programmed into the sampling flip-flop or the input receiver, a digital-analog converter (DAC) can be used to apply a controlled offset to the slicing function. Notice that a high-resolution DAC is not required—between six and eight bits represents a reasonable compromise between resolution and accuracy.

Various synchronous and asynchronous design alternatives are possible. For example, if a swept sampling time is desired, a variable phase-delay circuit could be inserted in the clock path to the flip-flop. The variable time delay could be based on the clock rate of the data and split a complete clock cycle into a uniform array of phase steps. Asynchronous alternatives could be implemented, provided there is sufficient dynamic range at the lowest operating frequency.

Critical to the implementation of a bit-compare sampling architecture is the implementation of a second parallel channel, connected to the same input source, but independently adjustable from the first channel. This duplicates the sampling capability of the core design and allows two samples of the input signal to be obtained from two different voltage and phase positions. One clock source is used for both channels, establishing a common timing reference for both channels. The circuitry in the second channel can be powered down when scanning is not taking place to lower overall power dissipation.

The parallel channel gives the scanning circuitry the capability of a bit-error-rate detector. The two results from the parallel sampling channels corrected for skew and compared on a bit-by-bit basis. When the designer sets a particular time period and accumulates results over that period, results are similar to a BERT output. Typical accumulation periods are greater than 2(16) (65,536) data bit periods to provide sufficient averaging and error rate resolution.

Using Embedded Scan to Observe Signals

The dual-channel sampling is particularly useful in comparing a reference sample to a swept sample. The hold/sample method entails holding one of the samples in the center of the eye diagram as a reference while scanning the other channel. By keeping the reference signal in an optimal position, the live data stream can be placed in the position with the lowest possible data rate. When the roaming channel has completed its scan, it can return to the optimal position for that channel to sample the data with the lowest possible BER. The scanning channel may optimize to a slightly different position due to the vagaries of transistor matching.
   
Designers could use a multiplexer circuit to switch between the two sampled channels, allowing the channel that was carrying live data to perform a scan while the channel that was scanned originally carries live data. This alternating scan method allows the eye diagram to be continuously scanned, even while carrying data on the eye waveform. Through such continuous scanning, the dual channels can continuously track the optimal position in the eye diagram, even as it drifts or fades.

The rate of disagreement between the two channels is equivalent to BER, and this rate will increase as the swept signal crosses signal edges in the data stream. The BER for any location across the eye depends on the type of data and the scrambling method used. Purely random data will toggle with even probability for each consecutive bit. Coding methods will alter the probability to reduce the run length of consecutive identical digits.

It’s important to emphasize the flexibility of having two independently controlled channels. The simplest scanning involves measuring either or both channels evenly across the voltage or phase array, but the shape of the data eye may dictate a special algorithm for scanning. This can give rise to an adaptive scanning process when adjusted over time. If a large number of voltage and phase conditions are tested, the BER count depth can itself become an important variable. For SONET (or even Ethernet) protection switching, real-time monitoring could be used. For a high-granularity level of detail, slower characterization also could be used.

We are not limited to the two dimensions of data used in contour plots. On 3D graphs of phase, voltage, and BER count depth, for example, changes in the slope of BER contours could be used to generate a diagram that was functionally equivalent to an equivalent-time sampling oscilloscope. With relatively noise-free signals, a significant amount of information on waveform edges could be analyzed in such a manner.

Obviously, embedded monitoring systems will have limits to accuracy and resolution compared to traditional test equipment. This is not a critique of the method so much as a realization of a conscious design tradeoff that must be made for signal visibility. Any circuit approach capable of being designed across a large number of input receivers will sacrifice some amount of information that could be gained by external test equipment. As embedded monitoring becomes more commonplace in the industry, however, the resolution and accuracy will be able to exceed that of standalone test instruments. The issues to be decided by the designers are the design, footprint, and cost-per-unit overhead that are encountered when embedding monitoring functions in high-speed transceivers.

In deciding on such tradeoffs, it is important to remember that finite frequency response in the embedded display will distort and limit a slew rate compared to a high-bandwidth oscilloscope. There will also be some compression of signal swing because of the limited linear range of the signal path preceding the variable slicing. At the same time, the mere absence of an in situ probe in an embedded monitoring design can eliminate perturbations from probe capacitance. A conscious decision on where to place the probe can influence the data obtained. If the signal is probed at the package pins, the time delay from external pins to internal termination can raise questions on signal integrity. Impedance discontinuities at the package-pin interface will be aggravated by probes placed at this location.

When the same circuits that are used for data acquisition are also employed for waveform scanning, these probe-based concerns disappear. By comparing a digital bit stream to a known reference, an embedded monitor provides eye-diagram results more analogous to a bit error rate detector than to traditional oscilloscopes. Even in circumstances where the data eye closes, embedded scanners still can gather data on the degree of closure because reference and scanning channels will register a finite error rate when located at the same voltage and phase position.

The Broad Application Space for Embedded Monitoring

For designers working on backplanes, line cards, and high-speed serial links, advantages can be realized at chip, module, and board levels from embedded scan. What’s more, the methodology carries fringe benefits in other applications, such as aiding remote monitoring for service providers and managers of large data centers.

In developing new generations of transceiver chips, scanning can help develop optimization algorithms for equalization blocks (or standalone equalizer chips). Waveform scans can be used to derive direct measurements of Q-factor, jitter, and frequency response. Regular analysis of the performance of a convergence engine would allow an external microcontroller to continue forwarding scan information to the convergence engine, or elect to override the convergence circuits.

Embedded scanning also allows designers to consider the characteristics of the sampling flip-flop in the CDR circuit. The finite frequency response characteristics of the flip-flop itself may not be taken into account in measurements from an external oscilloscope, or even within the convergence engine.

When designing boards for use in next-generation backplanes, or in specific I/O applications such as line cards, a fully populated chassis with multiple CPU and I/O boards can be analyzed for signal integrity without the use of special test cards and DUT cables. Because the CDR characteristics are directly observed, board designers can test not only the external compliance of the system to standards but also the internal signal acquisition margins of the receiver circuit inside a system.

The capabilities available to the bench engineer during product development and prototyping also are available for ongoing health monitoring of systems in the field. For the network manager, this means a board can notify a central switch in real time of potential failures so that board replacement can be planned for maintenance periods rather than in emergency replacements. For the service provider, this means that the data collected by a scanning circuit can be carried in packet headers and networked across MAN or WAN, allowing a remote terminal to analyze the data through operations, administration, and maintenance protocols commonly in use in public networks.

Obviously, the utility of such applications is only fully realized when embedded scan methods are adopted in a significant portion of the high-speed design community. Early developers of JTAG circuits had to develop a community before edge scan became commonplace in military-aerospace and real-time markets. As first-generation scan architectures evolve and their use becomes more widespread, potential applications grow as the user community increases.