Introduction

By IPC's definition, holes 6 mils (0.15 mm) or less in size on PCBs are called microvias¹. There are many advantages to microvia^1-16, such as much smaller pads can be used, saving on board size and weight; more chips can be placed in less space or on a smaller PCB, resulting in lower cost; and electrical performance improves, because parasitic capacitance is increased due to the smaller via length and diameter, and the inductance is reduced due to the shorter pathway created by the microvia compared to the plated through-hole (PTH). Combining microvia with via-in-pad (µVIP) saves even more PCB real estate^12-14.

In this study, the design, analysis, and modeling of a novel VIP substrate for housing a solder bumped flip chip in a CSP15 format soldered on a PCB are presented. Because of the special design, the substrate consists of a single core of organic material and two-metal layers of copper, and is manufactured with the conventional PCB process at very low cost. Furthermore, the vias are laser drilled, thus very small hole-size (0.15 mm to 0.1 mm) can be achieved.

The proposed substrate is used to support a functional 32-pin, low-power, high-speed static random access memory (SRAM). The assembled solder bumped flip chip in micro-VIP CSP package is soldered on a PCB. Non-linear time-temperature-dependent finite element method is used to perform the thermal stress and strain analyses.

The Structure

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In this section, the chip,µVIP substrate, solder bumped flip chip onµVIP substrate CSP, andµVIP CSP on PCB will be discussed.

32-pin SRAM IC Chip

Figure 1a and 1b.

The functional 32-pin SRAM (Figures 1a and 1b), is designed and manufactured at very high yield and low cost by United Microelectronics Corporation (UMC) on an 8" wafer. The major function of this SRAM chip is for very high speed and low power applications. The major characteristics of the chip for designing the Cu µVIP are listed as follows:

• Chip sizes are 5.334 mm x 3.662 mm
  
• Pad sizes are 0.075 mm x 0.075 mm
  
• Pad pitch is 0.195 mm (minimum)
  
• Chip thickness is 0.675 mm
  
• Chip pads are distributed on two shorter sides
  
• Two pads for ground and two pads for power

µVIP Substrate

Figure 2.

A novel VIP substrate has been designed for the 32-pin SRAM. Figures 2a and 2b show, respectively, the top and bottom sides of the substrate, which is a 0.164 mm thick bismaleimide triazene (BT) HL832 organic material with a high glass transition temperature. It can be seen from the top side that the traces from the peripheral pads are redistributed (fanning) inward and connected to the copper pads on the bottom side of the package substrate through the microvias. The diameter of the microvias is less than 0.15 mm and the diameter of the copper pads is 0.32 mm. The dimensions of the µVIP substrate are: 5.5 mm x 3.8 mm x 0.164 mm. The microvias are plugged in with non-conductive ink. The pitch of the µVIP is 0.75 mm.

Figure 3.

Figures 3a and 3b show the top and the bottom sides of the µVIP substrate for the 32-pin solder bumped flip chip SRAM. Figures 3c and 3d show cross-sections of the µVIP substrate.

Figures 3e and 3f show the X-ray photos of the µVIPs. It can be seen that, since there are no dog-bone pads, space saving is obvious. Also, since it is a very simple structure, lower cost is expected.

Solder Bumped Flip Chip on µVIP Substrate

Figure 4.

The assembly process of KVIP substrate with the 32-pin SRAM is very similar to that of the NuCSP reported in reference 15, except that in this study solder balls are mounted on the bottom side of the µVIP substrate. Figures 4a, 4b, and 4c show the cross sections of the CSP with the present µVIP substrate. Figure 4a shows the cross section along the chip pads. Figure 4b shows the cross section along the µVIP, and Figure 4c shows the schematics. Figures 4d and 4e show the cross section of the solder-bumped flip chip CSP with µVIP substrate. Figure 4f shows the X-ray photo, indicating the perfect alignment of the µVIP CSP assembly. Detailed dimensions of the µVIP will be shown in the finite element analysis section.

PCB Assembly of the µVIP CSP

Figure 5.

The assembly process of the µVIP CSP on the PCB is very similar to that of the conventional no-clean surface mount technology (SMT)17. Figure 5a shows the cross sections of the µVIP CSP PCB assembly. Because of the self-alignment characteristic of solder, PCB assembly of the µVIP CSP is very robust and can achieve high yields. Figure 5b shows the cross sections of a µVIP CSP PCB assembly with both solder bump on the chip and solder joint on the PCB.

Elasto-Plastic Analysis of µVIP CSP on PCBs

Figure 6.

Detailed dimensions of the KVIP solder joint are shown in Figure 6. The commercial finite element code ANSYS version 5.5 is employed in this study. A two-dimensional model is established using the 8-node plane strain elements. It should be noted that all detailed assembly structures such as the chip, underfill, solder mask, BT substrate, Cu µVIP, solder joint, Cu pads, and FR-4 PCB are modeled in the finite element analysis. Besides, due to the symmetry in the assembly structure, only half of the cross-section is considered.

Material Properties

The material properties used in this computational modeling are shown in Table 1. The copper µVIP is considered as an elasto-plastic material (yield stress = 54 MPa, yield strain = 0.0007, Young's modulus = 76 GPa, and the slope of the plastic curve is 0.1). The eutectic solder (63Sn-37Pb) is assumed to be a temperature-dependent elasto-plastic materials¹⁷. All other constituents are considered as linear elastic materials. The temperature condition for this study is shown in Figure 7 for the case from 25°C to 110°C.

Results

Figure 8.

A typical deformation of the µVIP CSP PCB assembly is shown in Figure 8. It can be seen that the maximum relative deformation (dominated by shear) is at the corner µVIP solder joint. This is due to the globe thermal expansion mismatch between the chip-BT substrate, PCB, and a raising temperature.

Figure 9.

The maximum von-Mises stress and accumulated equivalent plastic strain range at the corner µVIP solder joint and their contour distributions are shown in Figures 9 and 10, respectively. It can be seen that the maximum values in the corner µVIP solder joint are located at the corner interface between the lower left hand corner of the µVIP and the solder joint.

Figure 10.

However, these values are very small compared with those of flip chip on-board assembly without underfill or wafer level CSP. This is because the thermal expansion mismatch between the FR-4 PCB and the BT substrate is very small.

Figure 11.

The von-Mises stress contour distribution in the µVIP is shown in Figure 11. It can be seen that the maximum von-Mises stress is occurred at the lower left-hand inner corner, and is equal to 75 MPa. This is much smaller than the strength of Cu, which is in the range of 200 MPa.

Creep Analsis of µVIP CSP on PCB

In this section, in addition to the elasto-plastic strains, the creep strain of the solder joints on PCB is included. The 63Sn-37Pb is assumed to follow Norton's steady-state creep law.

Material Properties The Norton's steady-state creep relation, dy_crp/dt = B*exp{-DeltaH/kT}tⁿ (1) is used for the time-dependent creep analysis of the solder joints. In this equation, y is the steady-state creep shear strain, dy_crp/dt is the steady-state creep shear strain rate, t is the shear stress, DeltaH is the activation energy, T is the absolute temperature, k is the Boltzmann's constant (= 8.617x10-5 eV/K), and n is the stress exponent. For 63Sn-37Pb eutectic solder, the material constants of the Norton equation are given in Table 4.2 of reference 17, as n = 5.25, DH = 0.49 eV, and B* = 0.205 MPa-5.25sec-1, and is shown in Figure 12.

Figure 12.

In Figure 12, the constitutive relation of the 62Sn36Pb2Ag in terms of the Garofalo steady-state creep law obtained by Darveaux18 are also given. By comparison, it can be seen that the Norton (obtained by Pao¹⁷) and Garofalo (obtained by Darvaux¹⁸) for the eutectic solders for most of the operating temperatures are very different. For a given steady-state creep strain rate, the Garofalo model predicts much higher stresses than that of Norton. This is unexpected, since 63Sn-37Pb and 62Sn36Pb2Ag are very similar solder alloys.

Boundary Condition

Figure 7.

The temperature loading imposed on the µVIP CSP PCB assembly is shown in Figure 7. It can be seen that for each cycle (60 minutes) the temperature condition is between -20°C and 110°C with 15 minutes ramp, 20 minutes hold at hot, and 10 minutes hold at cold. Three full cycles are executed. There are two reasons for choosing this temperature profile: (1) the glass transition temperature of the FR-4 PCB is 120°C and we don't want to introduce additional failure mechanisms of the solder joint due to the degradation of the PCB; and (2) the behavior of solder below -20°C is not very well understood. Five full cycles are executed.

Results

Figure 13.

The deformed shape is very similar to that of the elasto-plastic analysis. Also, the location of the maximum shear stress and creep shear strain hysteresis responses is in the corner joint at the corner interface between the lower left-hand corner of the µVIP and the solder joint.

Figure 14.

For time dependent analysis, it is important to study the responses for multiple cycles till the hysteresis loops stabilize. The shear stress and shear creep strain of three cycles at the maximum location are shown in Figures 13 and 14, respectively.

Figure 15.

Figure 15 shows the shear stress and shear creep strain hysteresis loops for multiple cycles. It can be seen that the creep shear strain is quite stabilized after the first cycle.

Figure 16.

Figure 16 shows the time history of creep strain energy density at the µVIP solder joints' critical location for 3 cycles. The average creep strain energy density per cycle (DW) can be obtained by averaging the creep strain energy density of the last two cycles, which is 0.129 N/mm² = 18.7 psi. As expected, the values of DeltaW calculated in this study for the 73Sn-37Pb solder joints based on the Norton model¹⁷ are much lower than that for the 62Sn36Pb2Ag solder joints (0.189 N/mm² = 27.4 psi)16 calculated based on the Garofalo model¹⁸ which yields much higher constitutive values.

Thermal-Fatigue Life Prediction

Once DeltaW is obtained, the thermal fatigue crack initiation life (N_o) can be estimated from (Darveaux) Equation (13.35) of [18], i.e.,

N_o = 7860DeltaW^-1 = 421 cycles (2)

and the thermal fatigue crack propagation life (N) based on the linear fatigue crack growth rate theory can be estimated by (Darveaux) Equation (13.36) of [18], i.e.,

da/dN = 4. 96x10^-8DeltaW^1.13 (3)

or

N = N_o+ (a_f - a_o)/(4. 96x10^-8DeltaW^1.13) (4)

where a is the crack length of the solder joint; a_o is the initial crack length, which is assumed to be zero; and a_f is the final crack length. It can be seen that in order to determine N we need to choose an a_f. For example, if a_f = 0.347 mm (solder cracks through near the bottom of the Cu mVIP), then N = 10,515 cycles. On the other hand, if a_f = 0.433 mm (solder cracks through the diagonal of µVIP solder joint, i.e., from the corner interface between the lower left-hand corner of the µVIP and the solder joint to the lower right-hand corner interface between the upper right-hand corner of the Cu pad on the PCB and the solder joint), then N = 12,946 cycles.

It should be pointed out that due to a numerical integration scheme error in the old version of the finite element code ANSYS, Darveaux' thermal-fatigue life prediction equations may involve some errors¹⁹.

Thermal Cycling Test and Results

The solder bumped flip chip µVIP CSP on PCB assemblies have been subjected to a thermal cycling test with the temperature profile given in Figure 7. At the time of this writing, all the solder joints have survived for more than 2,200 cycles without any failure. The test is still ongoing.

Summary

A low-cost µVIP substrate for supporting a solder bumped flip chip in a CSP format has been presented. It is a single core two-sided structure with µVIP where solder balls are attached. Dog-bone pad structures are not needed and thus there is more space for routing.

The application of the VIP substrate is demonstrated by housing a SRAM device in a CSP format. It is found that the solder bumped SRAM chip is easy to assemble on the KVIP substrate, and the solder balls are easy to mount on the copper µVIP. Also, the µVIP CSP is easy to assemble on the PCB.

The thermal stress in the copper µVIP is calculated by a nonlinear finite element method. It is found that the maximum von Mises stress in the copper µVIP is much less than the strength of the copper. Thus, under the thermal cycling condition (25°C to 110°C), the copper µVIP should be reliable in most operating conditions.

The thermal-fatigue life of the µVIP corner solder joint is predicted by a creep analysis based on Norton's creep law and Darveaux's empirical equation. It is found that the average creep strain energy density is very small at the corner solder joint, and thus the joint can last for a long time.

Finally, the constitutive values of the 63Sn-37Pb solder based on the Norton model obtained by Pao are very different from that of the 62Sn36Pb2Ag solder based on the Garofalo model obtained by Darveaux. (Norton model yields much lower constitutive values.) Consequently, the predicted thermal-fatigue life of the corner solder joint from these two material models is very different. (Norton model yields much higher thermal-fatigue life.)

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