Not having DFM (Design for Manufacturability) checks in place for printed circuit board fabrication is a recipe for disaster. Potentially fatal flaws in a PCB design go undiscovered, yields are low, costs rise, and your customer’s critical new program is late to market. In today’s highly competitive environment, this kind of performance is not tolerated. DFM is a requirement prior to the fabrication process, enabling the customer to feel confident in the both the technical skills and manufacturing capabilities of their PCB supplier; however, Design for Manufacturability can take many forms. Ideally, the implementation and execution of DFM is a process that involves the customer early in the design cycle to not only uncover design flaws, but to deliver solutions.

Customizing the Front End

Front-end engineering groups—Product Engineering, Computer Aided Manufacturing (CAM) and Methodizing—should understand the value of customizing available tools. The first element in implementing a robust DFM process is having a capable CAM software package—one that performs all necessary functions of a DFM process. Out-of-the-box functionality may not, however, always meet the customer’s needs, so customization is key. For example, when comparing a customer’s netlist to provided data, CAM software often reports netlist discrepancies using pre-defined net names. Our customers initially struggled interpreting the results of the netlist discrepancies. In response, we created a script that takes the canned net name, determines the customer net name to which it correlates, and then creates a report based on the customer’s net name, reference designator, and pin location. This allowed customers to immediately determine if the discrepancies were designed-in and could be approved, or if they needed to be addressed via a new netlist or modified data. The automation created to enhance this CAM system is only as good as the folks creating it, and talented programmers add an incredible amount of value to any front-end group.

The DFM Process

Figure 1. DFM Process Flow: The most beneficial time to perform DFM analysis is prior to the final release of a customer's design.

It is critical, particularly where frequent customer interaction is involved, to crisply define and communicate the DFM process so that customers receive the same level of analysis and feedback every time. Using a web-based checklist to define, step-by-step, the process of performing a DFM is one way to deliver consistent performance against this goal. The checklist is driven by a selected route, which may be a non-recurring engineering job, a retool, an unclad mockup, or a DFM. Within each process route are process groups with specific web-based procedures.

The first step is data input. Here data is gathered and it's confirmed that the necessary files exist in a viable format to do a thorough one-time DFM analysis. Required data includes the layer data, drill data, a netlist file, and fabrication drawings. The ability to read native Cadence Allergro.brd files minimizes the amount of work required by the customer in order to perform a DFM analysis. Accepting .brd design files means that the customer needs only to output board fabrication data upon design release and not numerous times during their internal and external design review processes.

For many PCB fabrication facilities, the ODB++ format is usually preferred; however, the industry seems to still be working primarily with the more common Gerber data. When Gerber data is received it can add considerable input time because the layer data and drill data can be in any number of formats. Is the data English or metric? Is the format 2.4 or 2.5 or 3.4? Are leading or trailing zeroes omitted? Once the layer data format is defined, it's very possible that the drill data may be in an entirely different format. Creating templates for Gerber and tool aperture wheels will ease the communication process with the customer should there be any problems with initial data input or documentation.

With all data gathered and input into the CAM system, it’s on to the netlist analysis. If netlist discrepancies are found, a report is created, based on the customer net names, reference designators, and pin locations, and added to the DFM report. It’s beneficial here to research the discrepancies and provide feedback to the customer as to exactly where (layer and location) shorts exist.

The DFM analysis is then executed based on shop capabilities documented within the software. The results of the DFM analysis are reviewed and any issues are added to the report with visual aids to assist the customer in fully understanding the documented callout. Of the hundreds of possible callouts, spacing callouts are paid close attention. Based on the starting spacing, the applicable build specification dictates for finished annular ring, the copper weight of the layers, and the internal shop tolerance for registration, it can be determined if copper to copper spacing will need to be addressed at the DFM stage. This is the time to address the issue with the customer and decide what measures can be taken. Can non-functional pads be removed? Can pads be shaved? Can traces be jogged? These are common issues that need to be addressed, in particular when dealing with trace routing through high pin-per-square-inch connector footprints and densely populated daughtercards.

A customer documentation review is the next step in the DFM process. At this point the customer's fabrication notes are scrutinized for exceptions or issues that need clarification. The key component of the fabrication drawing is the stack-up, and more often than not, this is where most of the exceptions are found, especially with high layer count, impedance controlled product. The first step is to identify the impedance requirements and model the impedance.

The Signal Integrity development team’s baseline model was a numerical field solver that used the Method of Moments to calculate the impedance of a trace and an initial impedance coupon design necessary to automate testing. Boards were processed with various materials and impedance types (single ended, edge coupled, broadside coupled, etc.). Based on the results of numerous impedance coupon tests, correction factors were built into the baseline model. In order to further nominalize the results, traces were considered to be trapezoidal which is the true topography of a post-etch trace. Inputs to the model are dielectric thicknesses and tolerances, trace widths and, depending on the impedance type, trace-to-trace spacing, copper weight, and the dielectric constant. The impedance measurement requirement and allowable tolerance are included in the analysis.

Figure 2. Teradyne uses internally developed, java-based impedance modeling software.

A graph, showing the upper and lower control limits, allows the user to dictate what trace width tolerance is necessary, at the inner and outer layer etch processes, to be within tolerance. The impedance software is continually updated over time and allows us to build impedance-controlled product at high yields. This becomes more important every day as impedance tolerances are driven from what historically was plus or minus ten percent to plus or minus five percent.

Figure 3 and 4. Using a web-based checklist provides a standardized DFM report.

With the impedance modeled, an accurate stack-up can be generated around the impedance requirement. Ensuring that the core thicknesses required are standard product for the material vendor will mean less procurement delays. To determine what panel size will provide the best cost utilization, circuit size, the addition of all in-process coupons, and any other coupons required by the customer’s build specification are taken into consideration. Next, a script is executed that generates the expected retained copper for every inner layer based on the panel size, number of circuits per panel, and the number of layers. This number is used to dictate what pre-preg styles will be used to construct the board’s dielectric fills. All of this work generates a proposed stack-up in the customer’s DFM report with confidence that future modifications to the construction will be minimal.

At this point the DFM report is complete and ready for the customer. The feedback form shows each issue via a CAM application screen shot with the coordinates of the screen shot and a list of the layers displayed. Each screen shot is accompanied by text describing the issue and provides an area for the customers to add comments specific to each issue. If the customer has provided ODB++ fabrication data, the DFM report also includes CAD system synchronization scripts. These scripts can be saved by the designer to a standard location, bound to a function key, and, when executed, will display the same layers at the same location as displayed in the CAM software screen shot. With a defined process and a standardized DFM report, the PCB designer knows what to expect and, more importantly, is comfortable that all feedback will be addressed once and not in bits and pieces during fabrication.

DFM Quoting Demonstrates Potential Cost Savings

Combining DFM with the quoting processes can be a powerful tool. This provides the customer with a quote and a DFM report at the same time so that he or she understands, before the order is placed, whether there are issues that may cause the job to be put on hold unless they are resolved. Another benefit in combining the DFM and quoting process is the ability to provide conditional quotes. For example, a customer may request a process that doesn’t align with in-house capabilities; in which case the quote would include the subcontracted service and also show the potential cost reduction if the customer approves a final finish that is available in-house.

In another example, a request for high-speed material with a corresponding higher cost would generate two quote responses: one provided per the customer's material request and an another based on a standard material, such as FR4, with suggestions that would achieve performance requirements without increasing costs—such as back drilling at locations of higher-speed signals.

The goal of any DFM process should be to provide the customer with the DFM report in a timely manner—anything over 24 hours should be considered unacceptable. This means that the right personnel are required with the knowledge to perform DFM analysis quickly and flawlessly along with the right tools, well-documented capabilities, and a customer-aligned Production Engineering group to perform all DFM functions. In addition, performing the DFM as early in the customer's design stage as possible will help to add as much value as possible by providing not only problems, but also solutions.

DFM Execution

The earlier a circuit board or integrated system supplier can become involved in a customer's new program, the more the process will benefit all involved. Such an interactive process should begin with a Field Applications Engineering (FAE) team working directly with the customer at the system design stage.

The process begins with the customer having only a conceptual system design. The FAE integrates with the customer’s design team to understand the electrical and mechanical requirements. A suite of custom electrical, mechanical and thermal tools that allow for trade-off analysis of competing variables will help narrow the focus on the optimum solution. Examples of the tools used at Teradyne are link loss simulators, impedance and stack up generators, trace routing, current carrying and panelization optimizers.

Supporting the customer continues through the PWB layout stage, including proactive DFM reviews. DFM reviews occur during the layout process and prior to the start of manufacturing through face-to-face interaction or using online collaboration with the extended team. This interactive process will be enhanced if the PCB fabricator also produces assembled backplanes and is in close proximity to its customers. Fabrication facilities located in North American can be key here. However, even when it's not possible to get involved this early in a customer's design stage, DFM execution remains critical.

Treating DFM as an interactive process with the customer rather than only a required set of checklists and reports is key to success. Helping customers solve problems, realize performance gains, and get to market faster can’t be accomplished with static tools alone. Working directly with the customer to improve their product and the DFM process itself will result in a cleaner, more manufacturable design with higher yields and lower costs.

SIDEBAR: Reducing Cycle Time in Front End Engineering

Implementing a Design for Manufacturability (DFM) process can put stress on your front-end system in regards to cycle time and on-time delivery. OEMs expect a quick turnaround of the data once it has been launched. Reducing the cycle time in the front-end engineering area becomes extremely important in order to maintain customer satisfaction and allow for prompt and rapid response. There are three key components to reduce cycle time:

• Understand system capacity. What is the available hardware capacity and process time? The process time it takes to tool a job is the true capacity of the system and provides a goal for cycle time reduction.

• Understand information flow and how information is processed. Take into account all systems, people, and paper based checklists involved in tooling a job. The information flow also reveals all parties that may be involved when a job is being tooled.

• Develop and implement a data management system. Accurate data to investigate issues and develop solutions provides a starting point to reducing cycle time as well as maintaining good information flow.

The system capacity provides the baseline to which all cycle time metrics are established indicating the size of the opportunity to reduce the cycle time of tooling a job. When performing the evaluation, use one job as an example and understand what percentage of product it represents. The results of this test will illustrate the process time for a job that contains relatively the same features and how much each function contributes to tooling a job—revealing the true time it takes to tool a job from start to finish. Achieving cycle time reduction is an important and realistic goal regardless of how dramatic this variance may be.

By mapping out the information flow process (also known as value stream mapping) with the people who use the process; queue time or non-value added activities can be identified along with opportunities to combine functions and increase efficiency. Implementing a plan to address the opportunities is next. For example, a value stream map might show overlapping functions between CAM Technicians and Product Engineers. By cross-training Product Engineers on CAM tech functions, queues can be eliminated and the two functions will become better balanced in terms of process time, resulting in an improved flow of information and a reduction in cycle time.

In order to maintain any gains in cycle time reduction, establishing a data management system to provide a good flow of information and accurate cycle time data to monitor and drive improvements is critical. A good data management system can allow multiple functions to be performed in parallel rather than in series, which will result in further cycle time reduction. Capture processing data and cycle time data at each step to reveal more opportunities for improvement for both the methodology as well as the hardware.