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Happy Thoughts: Challenges for Designers During Uncertain Times
by Happy Holden
June 1, 2009

ARTICLE TOOLS
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Fig 1 Introducing Boundary Concerns
Incrementally While Doing Layout
Fig 1 Introducing Boundary Concerns Incrementally While Doing Layout


To say that we are in "uncertain times" is an understatement. But, we have a couple of things going for us PCB designers: electronics continues to innovate and solve problems—at a lower cost—and companies need to create new products to pull themselves out of this recession! The question is, Will you be part of that solution? Three business fundamentals drive most management and here is how you can contribute to:
  • facilitating lower PWB costs
  • improving performance and suggesting innovations
  • reducing schedules and providing "right-the-first-time" layouts
The key is to be the ‘last one laid-off’ by:
  • making yourself "invaluable!"
  • being more flexible and capable of doing more jobs than anyone else
  • being part of your company’s need to create new products if they want to "pull" themselves out of the recession
  • helping to change old paradigms. The time is now!
My first assumption is that "If you knew the answers, you would be using them!" So, this calls for "learning something new!" Or, now is the time to "learn from the best." Here are some of my suggestions:


Facilitating lower PWB costs

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To lower PWB costs, there are three ideas for low-layer count boards and two for high-layer count boards. These fall into the arenas of DFM, newer materials, panelization, and BGA breakout.


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Fig 2 (u.) Panelization of Three PNs
(l.) Panelization of Two PNs
Fig 2 (u.) Panelization of Three PNs (l.) Panelization of Two PNs
For boards <= 12-layers:
  • learn about new laminates from Asia
  • practice DFM
  • panelization of different PNs
For board’s > 12-layers:
  • lower layers with new BGA breakout (see my CircuiTree column from March 2009)
  • try HDI to lower layer count
Material and layer counts are the second- and third-largest cost drivers for printed circuit fabrication. Reviewing the laminate that the PCB is fabricated with and considering newer laminates from Asia that could be less expensive is a way to save on costs. Information on new materials is in the HDI Handbook and on my Mentor blog[1]. Reducing the layers on high-layer multilayers is sure to reduce costs, as well as doing a thorough check for manufacturability to look for ways to improve the fabrication yields.

Figure 1 shows the typical PCB layout process. There are eight opportunities in this process to stop and review the boundary conditions that affect cost, performance, and reliability. Learning about these boundary situations permits the opportunity to improve the process and the board. These critical boundary arenas are:
  • ECAD/MCAD interfaces
  • Signal and Power Integrity
  • EMI/RFI concerns
  • Thermal issues
  • DFM
Volume of the PCB fabrication order is the number one cost driver. One way to increase the order volume is to panelize more than one part number on the fabrication panel. This is something that you have to do, as it involves inventory, assembly, and test. But, as seen in Figure 2, if executed properly it offers the largest opportunity to reduce costs.


Improving performance and suggesting innovations

Improving performance is a large topic. But, a critical area is high-frequency electrical performance for the board in both signals and plane PDN. I would like to describe some of the work we have done at Mentor to help customers improve SI and PI. Other new trends are incremental design/validation methodologies and the improved use of constraint-autorouting, as well as re-use of circuits and DFT.


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Fig 3 SI/PI Information From Dr.
Eric Bogatin
Fig 3 SI/PI Information From Dr. Eric Bogatin
Here is where I suggest that you start looking for where you can learn these new topics. First, if you have not downloaded my new HDI Handbook, this is a good place to start. (This e-Book is available as a free download [1].) Chapter 4, "HDI Electrical Performance," is written by Dr. Eric Bogatin and he has many more resources available for learning, including 105 documents, lectures, and tutorials from his Web site. (His past Web series, "No MYTHS Allowed," is also available for download.)[2] Figure 3 shows a typical slide form one of his lectures. Dr. Bogatin’s current Internet site is http://www.BeTheSignal.com and it also has many free tutorials[2].

Another very useful design "toolkit" is provided by Kenneth Wood, owner of Saturn PCB Design in Deltona, Fla. His toolkit is shown in Figure 4 and provides software to calculate physical and electrical characteristics of vias and conductors; signal bandwidth and max. lengths; differential-pair impedances; padstack designs; drill/wire gauge conversions; min conductor spacing for voltages; and microstrip/stripline impedances.[3]


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Fig 4 Saturn PCB Design, Inc. Has
Free S/W to Use During Layout
Fig 4 Saturn PCB Design, Inc. Has Free S/W to Use During Layout
Another source of training and learning is to use Google and Yahoo to search the Internet for college classes in signal integrity, EMI Compliance, Design for Manufacturing or high-speed design. One such search yielded the EE166: High-Speed PCB Design course at Harvey Mudd College in Claremont, Calif. HMC has the distinction of being awarded as "One of the Top Undergraduate Engineering Schools in the U.S." In this case, it was the lecture notes and labs by Prof. Sarah Harris[4].

The IPC Designers Council and the IEEE are constantly running courses for designers.


Reducing schedules and providing "right-the-first-time" layouts

Last, to reduce schedules is one of "push left," "do it right the first time," and distribute more activities in parallel. Move critical activities and checks/audits up earlier in the design process. Find any problems or mistakes early. IF [errors] found in manufacturing, critical schedules and costs are bound to be impacted. Now is the time to "learn to use the autorouter correctly" and "how to apply signal and power integrity!"


Summary

Finally, if you are "surplused," "made redundant," "sacked," "displaced," "sacrificed," or just "let go," Mentor has the Displaced Worker Program.[5] You may take Mentor classes on a space-available basis, for free, and that includes online courses as well as in-class courses in Austin, Boston (Marlborough, Mass.), Chicago, Minneapolis, Dallas, Denver (Longmont, Colo.), Portland (Wilsonville, Ore.) and San Jose.


References

1. HDI Handbook and other tech papers, tutorials at http://communities.mentor.com/mgcx/community/pcb/pcb_blogs/happy_holden

2. Eric Bogatin’s "No MYTHS Allowed" at GigaTest Labs, there is 105 doc. www.gigatest.com/Publications/PubsIndex.jsp & www.bethesignal.com

3. Free PCB Tools (www.saturnpcb.com) – vias, conductors, signals, diff pairs, padstacks, min. conductor spacing & impedance.

4. University course lectures (like EE166 High Speed PCB Design by Dr. Sarah Harris of Harvey Mudd College-(www3.hmc.edu/~sharris/class/e166/)

5. Mentor’s Displaced Workers Program allows you to audit our training for free, go to http://www.mentor.com/training_and_services/training/dwp


Happy Holden
Happy_Holden@mentor.com
Happy Holden is the Senior PCB Technologist at Mentor Graphics-System Design Div., Longmont, CO. Happy is responsible for Advanced PCB consulting and new PCB Advisory Tools. Email:Happy_Holden@mentor.com

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