The best design is worthless if you can’t manufacture it. To be confident regarding manufacturability, it’s important to know manufacturing’s capabilities and limitations. There are organizations that work day and night to create guidelines and standards to make designs optimum for manufacturing.

These guidelines/standards will continue to change as capabilities, technologies, and processes improve and as product and manufacturing strategies evolve. CAM/CAD design guidelines incorporate all three major areas denoted by well-known terms: design for manufacturing, design for assembly, and design for testing. This article discusses basic CAM/CAD design guidelines used in today’s industry.

These guidelines aim to maximize manufacturability and reliability and reduce lead time. Most of the products follow a traditional process of development. However, with the prototypes EMS providers and contract manufacturers (CMs) design and assemble, there is always something new and challenging. The new challenges for design and fabrication are increasing signal speed. The introduction of such high-speed digital standards as SerDes, PCI Express, SATA, and FireWire pushed the performance limit to the maximum.

Enlarge this picture Table 1

The use of fine pitch components poses another challenge. For instance, 0.4 mm pitch is common, with 0.3 mm starting to show up. Plus, more mixed signal designs and environmental impacts (RoHS/WEEE) are presenting daunting issues. To successfully design a final product, there are many areas that need to be addressed and tradeoffs cannot be avoided. Conducting a design review by forming a team of individuals from all areas (i.e., manufacturing, assembly, and testing) optimizes the tradeoff analyses. However, a review needs to be conducted prior to layout design to avoid layout rework and to save time.

Table 1 shows the CAM/CAD design guidelines to be considered, while Figure 1 shows a basic flow of how a product is produced. Taking into account the process flow of an electronic product, from idea generation to end product, there are considerable reviews, tradeoffs, and predictive analyses involved.

CAM/CAD design guidelines focus on the layout design but practically encompass all aspects that are involved. Layout is the driving factor defining an end product. And CAM/CAD design rules drive and define layout considerations. Put another way, to document the design rules, one should know the design and test requirements and manufacturing and assembly limitations.

To achieve reliability and reduce lead time at an optimum cost, certain factors require careful scrutiny and careful attention to details when documenting the CAM/CAD design rules at the layout stage. These are board size, material, trace width and spacing, stencil challenges, drill challenges, surface finishes, and electrical parameters.

Board Size

Enlarge this picture Figure 2 Stackup Showing the Construction of a PCB

PCB manufacturers use panels to fabricate boards. Typical panel sizes are 16 x 18 in, 18 x 24 in, and 21 x 24 in. Panel size limits the maximum size of board that could be manufactured. Normal board spacing for routing is 0.3 in, plus there is typically a 1.0 to 2.0 in border on the board for tooling. To achieve optimum cost, board size should be selected to fit on a panel with as many boards as possible, with as little wasted board space as possible. By doing so, costs are reduced, especially when large quantities are involved.

The other extreme is that newer trends lead to greater densities and packing more electronic functionality into PCB designs. Thus, area available for mounting components becomes more precious and space on a PCB becomes even more valuable real estate. It’s no wonder that PCB layout becomes a nightmare for the designer as it requires a major effort to properly fit each and every component on a board while considering a vast assortment of electrical constraints driven by today’s high-speed technologies.

Board area is not the only factor. Width-to-length ratio (form factor) is also critical to consider to avoid warping during assembly. Similarly, board shapes, driven by packaging mechanical limitations, are such that they pose great challenges for assembly and fabrication.

Fabrication tolerances become critical in some instances. For example, an issue crops up when a board with the slightest increase of 2 mils in thickness is made unusable. To avoid such issues, manufacturing tolerances should be considered while spelling out the notes in design. Placement has to be performed considering the area that the pick and place machine requires. The cost of a fixture or creating a rectangular shape with route and retain to be scored after assembly should be compared before the start of fabrication.

Another important parameter is board thickness. When not specified, the standard thickness and type of board is 0.062 in FR-4. Other typical board thicknesses are 0.010 in, 0.020 in, 0.031 in, and 0.092 in. Board thickness plays an important role to decide the stackup with impedance requirements. Board thickness is also governed by prepeg material.

Material

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Selecting material that meets performance characteristics and minimizes manufacturability issues such as bow, twist, and mis-registration is very critical. Raw laminate is a major cost component in a multilayer board. To optimize cost, laminate construction around standard base materials is used to achieve maximum material utilization based on the usable area available. When specifying dielectric thickness, required for impedance reasons, the designer should know the construction.

There are three main components that make up the PCB. One is copper foil. Sheets of copper foil are incorporated into the outer layer of the PCB placing it on the prepreg to create the outer layers. Second is core, commonly called C-stage or laminate. This is fully cured glass-epoxy material with copper laminated to both sides. This is used for internal layers. Prepreg is used to separate multiple layers. This is commonly called B-stage or bonding sheet. This consists of glass and uncured resin that is able to flow when heated. There is no copper attached to this material. It is used to provide isolation and thickness between core layers and outer layer foil layers and to flow around the copper features on the adjacent layers (see Figure 1).

The new trend toward environmentally conscious manufacturing (ECM) to utilize designs and processes that are less wasteful often limits the choice of design engineers for selecting material. However, there are certain practices that help ECM and do not impact cost. One is the choice of solder mask that affects the amount and toxicity of the solvent used and emitted. The choice of anti-tarnish instead of hot air solder leveling (HASL) reduces the use of lead and emission from flux and fusing oil. Another is the use of the lightest copper weight, 0.5 oz, which results in the least use of chemicals and generation of waste byproducts.

Trace Width and Spacing

Enlarge this picture Figure 3 Stencil Showing the Process of Printing Paste Using Stencil

Most fabrication houses use chemical and photographic processes to produce a PCB. During this etching process, the etchant, due to impingement forces, removes copper downward and laterally. The tin etch resist in the case of outer layers and the dry-film etch resist in inner layers establish the original line width but cannot avoid eventual undercut of this boundary.

This process puts a limitation on the minimum width of a trace and the minimum spacing between traces in accordance with the copper weight used. If a trace is made smaller than this minimum width, there are chances that it will be etched out during the etching process and, hence, will create an open connection on the board. Similarly, if the traces are closer together than the minimum spacing, there is great chance they will short as there won’t be enough space to etch copper out.

These parameters are usually specified as x/y, where x is the minimum trace width and y is the minimum trace spacing. For example, 4/6 would indicate 4 mils minimum trace width and 6 mils minimum trace spacing. Nowadays, most of the fabrication process is such that 5/5 does not pose any challenges. However, with values as small as 2/2, newer technologies like direct laser imaging are required. Also, one should always consider that a board has to be assembled and, especially in prototypes, rework or manual soldering is required most of the time. Pad size and spacing of copper from the pads and drill play a major role when it comes to assembly.

Stencil Challenges

Flux determines the activity level between the flux and solder paste. Failure to provide adequate heat to ensure sufficient flux activity prevents the balls from collapsing correctly. A thermal profile should be adjusted considering PCB layer count, the number of planes inside the board, the type of PCB material used, component types, component density, and PCB thickness, as well as its length and width to ensure optimum reflow for perfect solder joints.

In addition to correct reflow, correct stencil printing (Figure 3) is critical to a successful PCB assembly. Stencil thickness, aperture sizes, and the use of framed or nonframed stencils all play a role in the accurate dispensing of solder paste onto the board. Too much paste can create shorts between fine-pitch BGA balls. Conversely, too little paste can result in insufficient wetting and cold solder joints.

A broad set of rules has been devised for stencil specification as every board is different in nature and the factors that drive the aperture size and thickness vary on the same board. Put another way, fine pitch components pull toward smaller pad sizes and thinner foils, whereas this might create inadequate paste for some heavy components. The new technology that is evolving for the stencil is to actually create a sheet with openings and not cut apertures in an existing sheet. This will allow EMS providers and CMs to achieve different thicknesses at different locations on the same stencil.

These factors comprise one side of the assembly story. The other is that BGA-
associated solder defects are often tricky to detect due to shrinking BGA sizes and the fact that collapsed balls cannot be seen by the human eye, even with the help of a magnifying glass. For this reason, the design should be laid out in such a manner that it is convenient to test the design.

Today’s modern equipment such as bed of nails and flying probe allow test points to be very precise. The method to test fine pitch BGA is to use via in pad design with pad on the solder side unmasked so that these could act as test points. However, via in pad can unfortunately be the reason for solder void formation. That’s the reason SMT design engineers do not like to see via in pad designs because it impacts reliability and yield. This technique also poses challenges to fabrication as drill and plating becomes tighter.

Drill Challenges

When considering drill and pad sizes, a ±3 mils tolerance is typical for drill up to a 10 mil size. Some are tighter, where tolerances could be +/-1.968 for a 6 mil or smaller sized drill. There are specific guidelines for drill hole and pad sizes. For instance, a 10 mil drilled hole must have at least 18 mil annular ring, allowing for a 4 mil annular ring. Larger annual rings are preferred to create a more solid pad joint that can withstand several component extractions and placements, as well as being able to undergo multiple reflow cycles without incurring problems.

Surface Finishes

A surface finish provides a coating over the outer layer copper that prevents oxidation and provides an electrically conductive surface. This surface has two generic functional requirements. The first is to provide a solderable surface for connecting components with solder. The second function is to attach a component without soldering, such as a wire bond or press-fit connector. There are several tradeoffs involved with the surface finishes, including shelf life, cost, reflow cycles, and solder joint flatness. While each finish has its own benefits, in most cases, the process, product, or environment will dictate the surface finish that is best suited for the application. This is another factor that needs the involvement of all stakeholders—designer, fabricator, assembler, and even end user (environmental issues)—to select the best finish for the specific product design.

The following provides a brief overview of different types of surface finishes. HASL is the most prevalent conductive protective coating used in electronics. A thin solder coating is deposited onto all exposed copper pads. Boards that have been HASL leveled will have bright silvery pad coloration. However, with the environment-friendly culture of RoHS, this finish cannot be used.

Organic solderability preservative (OSP) process coats a very thin coating of an organic material that inhibits copper oxidation. It is so thin that it is nearly impossible to see and measure. The organic material is removed by the assembly flux. Boards that have been OSP coated will have bright copper pad coloration. This has less shelf life and can withstand up to three reflow cycles.

Electroless nickel immersion gold (ENIG) process plates a thin coat of nickel covered by a thin layer of gold. The gold provides a very good solderable surface. When components are soldered onto these pads, the gold diffuses into the solder joint. After HASL, this is the most prevalent coating as it increases the shelf life, can withstand six reflow cycles, and increases the flatness for press fir components.

Electrical Parameters

Enlarge this picture Figure 4 Impedance and the Effect on Signal With and Without Controlled Impedance

The previously explained factors are not only responsible for manufacturability but also impact board functionality. All electrical characteristics should be considered prior to making sure that a board is functional. Today’s high-speed chipsets transmit data above +12 Gb/s and rise times going below 30 ps. For this signal, even small parasitic inductances and capacitances can degrade a signal and introduce noise. Even the slightest discontinuities can cause signal integrity problems. The three primary characteristics that need to be considered by a designer are impedance, electromagnetic interference (EMI), and power stability.

Impedance is derived from three basic elements: resistance, capacitance, and inductance. By definition, it is the resistance to flow of current with phase difference from voltage. To avoid signal integrity issues, impedance of the source must be equal to the impedance of the trace. Impedance mismatches allow the digital signals to reflect between the input on the receiving device and the output on the transmitting device. Reflected signals are bounced back and forwarded between the two ends of the line until eventually they are absorbed by resistive losses.

Impedance mismatch (Figure 4) can be created by improper termination of a high-speed signal and stubs in layout traces and vias. Signal impedance can be managed by controlling a trace’s characteristic impedance. The factors used to control the characteristic impedance are trace width (W) and thickness (T), material dielectric constant (_r), and height (H) between the trace and reference plane.

Reflected signals introduce ringing on the signal sent across the trace. Ringing impacts a signal’s voltage level and timing and can severely corrupt the trace. A mismatched signal path can cause the signal to be radiated into the environment. If stronger signals are present in the environment it can cause EMI. By definition, EMI is an undesired electrical signal within the elements of a circuit, which is produced by coupling from another signal external to the circuit or from elsewhere in the circuit. The FCC has defined rules for products and the allowable EMI, hence it is extremely important that this should be considered at design level or else the product could fail the EMC.

To find the solution to this problem, the cause must be studied. It’s known that current in a circuit flows in a closed loop and is the same everywhere. So if the signal current generates EMI, the return signal also creates an EMI that is similar in magnitude and opposite in direction. If the signal and its return are close enough, the radiation generated by both cancels each other. Hence, to reduce EMI, the loop area has to be minimized by creating plane underneath the trace.

Another important characteristic that needs to be considered is the stability of the signals. This is crucial when mixed signal designs are involved. The key to this is proper separation of analog and digital components, planes, and traces.

Conclusion

CAM/CAD design rules are derived from design and test requirements and manufacturing and assembly limitations. There are always some tradeoffs in following the best practices, standards, and design guidelines. If emphasis is placed on reducing board size, the real estate will decrease and might force a PCB designer to violate placement constraints and, hence, reduce yield. Similarly, if the best available material and surface finish are emphasized for better quality, those might affect the product’s overall value.

To achieve optimum results, design tradeoff analyses performed in conjunction with these design guidelines must also take into consideration manufacturing strategies and business direction of producing all products. Concurrent engineering interaction is essential for optimum design results and product life-cycle costs. Concurrent engineering and design verification may increase the length of the design phase slightly, but this effort can reduce both the number of design cycles required and the overall time to market or time until production release. The key is that it requires a team approach to be successful.