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For nearly 20 years, design-for-test rules have been used in printed circuit board designs for in-circuit test (ICT) pads. Recently however, it is becoming more challenging and even impossible for designers to include ICT test-pads in their designs due to increasing PCB densities. There have also been concerns among designers about incorporating ICT test pads into the high-speed sections of today’s leading-edge designs. As a result of these changes, some are questioning the long-term viability of ICT in today’s high-speed/high-density PCB environment. A new ICT probe technique called “bead probes” has been introduced to address these challenges.

The traditional ICT probing technique uses a “bed-of-nails” fixture to aim hundreds or thousands of probe contacts with each board. A sharp chisel or spear tipped probe penetrates the soft solder on a test pad or via and makes reliable electrical contact. The design rules establish these access points and ensure “testability.” Reliable ICT implementation requires that the test target be of a certain size and that the probes themselves not be too close together. Established research has demonstrated that targets as small as 35 mils can be tested reliably with test probes no less than 50 mils apart. As board density continues to increase, these targets are shrinking, making it more difficult to reliably access them with traditional ICT techniques.

The “bed-of-nails” approach is also prone to unreliable testing results with high-speed designs, in which it is common to have trace widths as small as 3 mils. With gigabit data transmission rates and controlled impedance, designers are understandably reluctant to include a probe target such as a 35-mil test pad that could interfere with the design performance.

A New Approach

In 2004, Agilent Technologies developed a new approach to ICT that essentially turned the process upside down. Compatible with any ICT platform, this new technique called “bead probe” can be compared with throwing a dart-board at a dart. Instead of placing test targets on a board and hitting them with probes, this technique essentially mounts the probe on the board and the test target on the fixture.

Figure 1. For the new bead probe method, a small hemi-ellipsoid bead of solder is added on top of a trace.

The bead probe method requires the addition of two steps in the design process to incorporate a “bead probe,” a small hemi-ellipsoid piece of solder, nearly invisible to the human eye, on top of a trace. The bead probe is the same width of the trace and its height is only a few mils making it higher than the mask.

Bead probes can be fabricated with well-established PCB manufacturing techniques, made from solder using standard paste-reflow solder processes. ICT fixtures can be easily updated or adapted for use with bead probes with resulting probe resistance and contact reliability similar to traditional spear probes with solder-coated test pads.

Figure 2. Solder bead flattened after contact with the flat-faced ICT probe.

The key to this good contact performance is displacing the contaminants that naturally build up on the surface of solder. With a bead probe, this displacement occurs when the flat-faced probe flattens the “sharp” hemi-ellipsoid of solder. This flattening is a function of the yield strength of the solder, the spring force of the fixture mounted probe, and the final area of the flattened surface of the bead probe.

Bead Probe Fabrication

Bead probes are manufactured in the same way as all other solder features. The solder mask is opened up over the trace wherever a bead is needed.

Figure 3: An example stack-up of trace outline, solder mask and stencil holes is shown.

The solder flows and then freezes, and wicks up onto the copper trace due to the affinity of solder for copper and lack of affinity for the mask. The height of the bead is controlled by volume. A typical solder paste is roughly 50 percent flux that will vaporize during reflow. Thus roughly half the volume of paste will be deposited as solder. The solder stencil aperture is sized to assure that enough solder is deposited to later bead up via surface tension to a height that exceeds the surrounding mask.

The solder mask hole is a obround hole (rectangular with rounded ends) of width W and length L center to center as shown. The width will be equal or less than the width of the trace and the length should run in the same direction as the trace. The area of the obround hole, which exposes copper, is:

The solder stencil hole is a square (side length D) rotated 45 degrees to the trace and centered on the bead location. This hole is larger in area, D2, than the mask hole. The rotation maximizes the area of copper that will receive solder paste, while the square is a preferred geometry for reliable stenciling. Some paste will be applied to the solder mask, but this paste will flow onto the copper when melting. The thickness T of the stencil will also determine the amount of solder paste that is applied. The past volume applied to the board will be TD2, which after vaporizing the flux will yield TD2/2 volume of solder.

Given W, L, D and T, we can calculate the approximate height H of the resulting bead as follows. Divide the solder volume by the exposed copper area, or:

If we are given W, H, D and T, then we can calculate the approximate length of the bead as:

Beads are (approximate) hemi-ellipsoidal structures. When a hard, flat surface is pressed onto them, the initial contact is a point with infinite pressure, so the solder must move. As the surface yields, an area begins to form that is basically an ellipse with a semi-major axis A that runs along the length of the bead, and a semi-minor axis B that runs along the width. The area of the ellipse is pAB. The area continues to increase until it is able to support the spring force. Using the yield strength of solder expressed in ounces per square mil (0.08), we see the areas needed to support a force in the following table:

Table 1. Area needed to support probe spring force.

The semi-minor axis of a bead is often constrained to the width of the trace it sits upon. If a bead is too small, the surface area needed to support the spring force might be larger than the bead itself, implying that the bead would be catastrophically crushed out over the solder mask.

If the bead is overly large, then the surface yield area may not displace enough solder to move oxides. The semi-minor axis should not exceed 50% of W (W > 2B) as shown in Figure 4 as this would imply bead crushing.

Figure 4. Top-view of a flattened bead.

Table 2 shows semi-major axis lengths needed to support spring forces for some bead widths and forces. For low spring forces, beads must be very small or there will not be much surface yield on the bead. For all beads, the semi-major axis must be smaller than half length of the bead, as was true for the semi-minor axis versus width. Again, using the 50% factor, each bead length should be greater than 2 times the semi-major axis length (L >2A).

Table 2. Semi-major axis lengths needed to support spring forces for bead widths.

Bead widths less than 4 mils will be more difficult to build reliably, since the solder mask registration on a correspondingly narrow trace will become a factor. Also, the width to height ratio will become a factor, since the bead must be tall enough to clear the solder mask by several mils. The solder mask itself supports the sides of a bead, but building tall skinny beads may not be reliable.

Real World Implementation

Agilent tested the bead probe approach in a real PCB design to evaluate its effectiveness in a real-world implementation. The board selected was an ideal candidate for an alternative ICT technique. The board design was very dense, allowing for limited use of traditional ICT probing locations. Facing time-to-market pressures and planning to outsource manufacturing, the manufacturer was concerned that the lack of ICT access would ultimately impact the profitability of the project.

The initial challenges in this trial arose out of the CAD issues. Bead probes are built as CAD library elements as obround surface vias. Most CAD tools do not allow for rotating round objects such as vias, because it is not typically required in board design. In order to allow for manipulating bead probes in the design, it was necessary to develop separate bead probe geometries in all necessary orientations and sides. (Agilent has made available the sample bead probe ASCII geometries it created for this trial in Mentor Graphics Board Station EN2002.

There were also CAD-related problems with the first prototypes manufactured. Due to a bug in the CAD layer mapping to Gerber data results, there were no stencil openings in the mask and therefore, no solder on bead probes. For the second prototype, the solder stencil vendor mistook the bead probes for fiducials and deleted all of them. For the third prototype a new solder stencil vendor deleted some bead probes, requiring some manual rework.

For this trial, traditional ICT test vias were used wherever possible, so of the 360 bead probes in the design, 74 were selected for ICT and used with 4 oz. flat-head probes.

As seen in the difficulties experienced in this trial, using contract manufacturers requires additional training and communication when the bead probe technique is adopted. Temporary visual inspections must be added to the Gerber data, the finished solder stencils, and post-reflow PCAs, to ensure that the quantity, quality, and location of bead probes match expectations. ICT tests utilizing these bead probes should use industry-standard test ‘hardening’ techniques, to ensure that these device tests remain stable and portable in a production ICT environment.

Conclusion

Agilent Technologies is working with OEMs to further qualify this process in production. Early trials show that bead probes can be manufactured using standard SMT processes and supply chains and they provide a reliable probing strategy. In initial uses, a conservative approach, such as the one used in the trial described here, is recommended to minimize risk. By adopting the new bead probe technique, manufacturers with any ICT equipment will be able to extend the life of their existing equipment and reliably test today’s high-speed, high-density PCBs.