Introduction

Buried capacitance has been used for sometime now in sophisticated PCB designs. The most widely used product for buried has been and still is ZBC 2000™ which is patented by the Sanmina Corporation. Conceptually this product consist of one or more innerlayers with a two-mil FR4 core. Each innerlayer forms a sheet capacitor of approximately 500 pico-Farads per square inch. The original purpose of the technology was to replace the surface by-pass capacities with an internal alternative and thereby provide additional outerlayer real estate for routing and active components. Later it was also found that a properly designed buried capacitor structure was an effective method for containing EMI radiation.

Recently, the industry has seen an evolution of new buried capacitor materials with higher dielectric coefficients. In most cases, a higher dielectric coefficient is desirable since the strength of the capacitor is directly proportional to the dielectric coefficient. This is achieved in some cases by loading the dielectric with particles of ceramic or barium compounds. In other cases, a dielectric medium with a high dielectric constant such as polyimide is used. The dielectric coefficient of the ZBC2000™, material FR4, is approximately 4.0; for the more recent materials, the dielectric coefficient in cases exceeds 20, providing a sheet capacity in the micro-Farad range.

The compatibility of these materials with existing buried capacity designs has raised serious concerns for the designers. A particular concern is the impact on the electrical performance of the board by altering the dielectric constant of the buried capacitance layers. The discussion below will focus on an analytical analysis this issue.

The Issues

There are several perceived concerns regarding the impact on the electrical performance of a PCB by altering the buried capacitance material. Some of the first order issues that come to mind are:

• Supplying charging to the load

• Capacitor recovery

• Propagation delay

Each of these issues are discussed below.

Supplying Charge to the Load

The charge necessary to drive an active device is normally provide by a so called by-pass capacitor; in our case a sheet capacitor buried within the board and connected to the V_cc pin of the device. The issue is the impact of changing the dielectric material of the capacitor an thereby alter the dielectric coefficient.

A simplified model of the charging phenomena is shown in Figure 1, which depicts a circuit composed of a capacitor (C) with an initial charge of CV_e and a load, which in this case, is simply a resistor. At time t=0 the switch is closed and the capacitor discharges into the load, i.e., resistor.

The flow of charge (Q) to the load is described by the differential equation:

The algebraic solution is:

The denominator RC is often referred to as the time constant (τ)

We are for the most part concerned about flow properties the instant that a power surge is required by the load; in our analogy this corresponds to the instant that the switch is closed or when t=0.

The rate of flow of charge is

Obviously then, the magnitude of the initial surge of current from the capacitor to the load is independent of the size of the capacitor. The advantage afforded by increasing the strength of the capacitor as seen in (4), is to increase the time constant τ, thereby reducing the decay rate of the current flow and increasing the total charge available to the device.

Two observations can now be made concerning the issue at hand. (1) Varying the strength of a buried sheet capacitor will have minimal or no effect on the initial flow of charge. (2) The amount of charge available to the device within a specified time increases as the capacitance of the sheet capacitor increases. Consequently, replacing the buried capacitor material in an existing design with another that has a higher capacitance will from this perspective improve the performance of the design.

Recovery of the Sheet Capacitor

After a device has drawn charge from a capacitor, there is a finite time before the capacitor can support another demand for charge, which raises the second concern. What is the impact on the recovery time caused by replacing the buried capacitance material in an existing design with another of a different capacitance?

A first order analysis can be performed by partitioning the buried sheet capacitor into an active area where charge has just been drawn by a device and the rest of the capacitor that now acts as a near infinite source of charge.

The model is shown in Figure 2. Capacitor C₁ represents the area that has just discharged and C₂ the surrounding area of the buried sheet capacity.

Initially, the charge on capacitor C₂ is Q₀ and C₁ is completely discharged. The flow of charge from C₂ to C₁ is given by:

The time to reach equilibrium between the two capacitors is determined by the time constant τ. For our purposes C₂ >>C1 and 1>> C₁/C₂. Consequently:

With (11) we are now positioned to estimate the variation in the recovery time for different dielectric materials. For our circumstances, the capacitance of the buried sheet capacitor will range form 500pF/in² up to 2 nF/in², depending upon the dielectric constant of the material. The electrical resistance of the half-ounce copper cladding is approximately 1.0 m_/square. A reasonable value for the size of C₁ would be several square inches. The surrounding copper that is effectively charging the area C₁ is several squares. Some typical values would be, 2.0 square inches for the discharged area -C₁ and 5 squares for the area of the charging the capacitor. Then the time constant RC₁ will range between 15 and 60 pico-seconds depending upon the dielectric material. If we assume that three time constants will be required to reach equilibrium, then the time required is between 45 and 180 pico-seconds. Even for systems operating in the gigahertz range, it is doubtful that a variation of no more than135 pico-seconds in the recovery time will have a noticeable impact. Consequently, replacing an existing buried capacitance layer with another with a different dielectric constant should not present an issue so long as the dielectric constants are in the range of 4 to 20.

Propagation Time

When an electrical signal is initiated, a finite amount of time is required for it to traverse the circuit between the buried capacitor innerlayer and the load. The issue here is, will a change in the dielectric constant of a buried sheet capacitor create a significant change in the time required for charge to travel this distance.

An electrical pulse moves at the speed of light in the associated dielectric and can be calculated by dividing the speed of light in a vacuum by the dielectric constant. In this case, the charge moves from the buried capacitance layer through a via connected to the device. The surge originates at the juncture of the via and the buried capacitance layer. The dielectric material surrounding the via is not affected by altering the dielectric of the buried capacitance material; therefore; the charge moves through the via at the same speed irrespective of the dielectric used in the buried capacitor layer. Here again, altering the dielectric of the buried capacitance layer should not affect the propagation speed between the layer and the device.

Summary

The impact on board performance caused by replacing an existing buried capacitance layer with another using a different dielectric material has been explored. The particular issues are, charging the load, capacitor recovery and propagation time. The analysis shows that neither the recovery time nor the propagation speed is significantly impacted. It was also found that the initial flow of charge to device will be the same. The major affect will be in the equilibrium charge delivered to the device, which is in direct proportion to the dielectric strength of the capacitor.