Introduction

The use of thin dielectric substrates to provide Embedded Capacitance has been driven by the need to improve electrical performance of Printed Circuit Boards. Current standard capacitive material used in the industry is mainly the 2mil dielectric thick material, mostly utilized for telecom and networking applications [1] . For this particular high-end application of PCBs, embedded capacitor technology has been utilized to reduce the inductance between the chip and the power supply. This improves the electrical performance of the distributed capacitance, enhances signal integrity, and reduces impedance at high frequencies while dampen noises.

A number of papers have been published regarding development of materials for embedded capacitors and advantages of incorporating embedded capacitor in PWB. From the electrical performance standpoint, demand is increasing for thinner capacitor material, as low as 10 micron, as the signal frequency increases.[2] In this paper, considerations of copper foil and dielectric resin properties (which make up the capacitor material) are discussed. Also, fabrication of the thin film capacitor material incorporating into PWBs and performance of electrical performance using the materials are described.

Investigations

Embedded capacitance materials are constructed from two metal layers (usually copper foils) and dielectric polymer film layer in between. In order to design the construction of the capacitance material, properties of the copper foil and dielectric layer will be the “keys” to determining the performance of the capacitance materials.

Investigation of the influences of copper foil, dielectric type and dielectric thickness has been conducted to design the construction of the thin capacitance material.

1) Copper Foil
As previously described [3] different types of copper foils were investigated for their influence on the performance of the capacitance material. What we wanted from the foil was not only good performance from the normal characteristics (peel strength, HTE, etc.) but also good capacitance value and insulation resistance.

Copper Selection Process

We examined four lectro-deposited (ED) and one wrought (rolled) foil. Peel strength, capacitance of the substrate and High Potential (Hi-Pot) Voltage Testing (at 500 Volts DC) were compared. As mentioned in our previous paper [3] it was found that the higher the profile of the copper foil, the higher the peel strength as well as the capacitance values. Unfortunately, increasing the profile also reduced the yield at Hi-Pot testing.

Copper Foil Decision

When the balance of properties was examined, it was determined that for capacitor material down to 16 micron, a version of reverse treat foil (RTF) gave both good mechanical and electrical performance. For 12 micron material and below a special very low profile (VLP) foil was required.

Dielectric Resin

One of the challenges for thin capacitive material is the physical property of the dielectric. The thin dielectric must be tough and flexible in order to withstand processing through PWB manufacturing process. Another challenge for thin dielectric is the insulation reliability, such as hi-pot test and electro-migration.

Dielectric Selection Process

Table 1.

As indicated previously [3] we looked at two types of unfilled dielectric materials. One type (A) is a conventional and industry standard epoxy resin system. Another type (B) is a proprietary, modified resin system, designed for capacitive material. With these 2 types of dielectric systems, substrates were prepared to evaluate physical properties and insulation reliability.

Resin toughness is an important property to determine the capability to be processed through PWB manufacturing steps. If the resin’s toughness were too weak, since the resin thickness is so thin, the resin would break a part during the etching process. As shown in Table 1, resin type B exhibited about 4.5 times higher tensile strength than A, which signifies the advantage of resin type B for endurance during PWB manufacturing process.

Electro-migration

Table 2.

As the dielectric layer thinner, there is a concern regarding insulation reliability between the layers. Electro-migration tests were conducted at the condition of 85C/85%/35V, for two different resin systems. The dielectric thickness was prepared at 10µm. The result is shown in Table 2.

Although resin type A lasted only 682 hours before electrically shorted, resin type B lasted for over 1000 hours. The differences in ion contamination, moisture absorption and polymer structure seems to be influencing the electro-migration endurance period.

Dielectric Decision

Table 3.

Based on the above results it is obvious that resin B is the best option for the dielectric material.

Description of the thin capacitance material
Based on the investigations of copper foil and dielectric resin properties, suitable copper foil and resin type was selected to construct/manufacture 12, 16 and 24µm dielectric thickness capacitive material. Characteristics of the developed capacitive materials are listed in Table 3.

Processing of the Capacitance Material

Three different PCB fabrication facilities have processed
the substrates. The trials were conducted on thin
film capacitance materials of 24, 16 and 12 µm dielectric thickness,
to see the capability of processing the material with existing conventional manufacturing equipment.

1) Pattern Formation
One of the major design criteria for the material was to be
able to be processed through the standard inner layer process.
The typical process consists of:
1. Chemical Pre-clean
2. Dry Film lamination
3. Image Expose
4. Develop, Etch and Strip (Dual sides)
5. Black oxide or Alternative

Due to the tough and flexible nature of the resin, the material was processed without being damaged. This included not having the clearance holes “blow out” during etching or having the border detach from the circuit. This is not the case for many thin capacitor materials.

Although, processing thin capacitance material can be challenging and may need modifications or adjustment to the process, the material was capable of processing through the conventional PCB manufacturing steps. This was proven at all three fabrication facilies.

2) Hi-Pot (High potential) Test
The patterned laminate was tested to Hi-Pot test. All the panels passed the 500V test, including the 12 micron dielectric thickness material. The high yields at inner-layer test are due not only to the construction of the material, but by having any marginal material caught at the substrate manufacturer by pre-testing.

Figure 1. Dimensional stability during the process.

3) Lamination
Scaling is a very important parameter for multilayer lamination. Figure 1 shows the measured result of the movements of the distance between the holes during the process. As it can be seen, thin capacitance material’s movement was equivalent to that of 50µm (2mil) core material. This is most likely due to the fact that since most of the copper is retained, the dielectric thickness has little effect on the scaling. Hence, as a first trial the scaling factor for the thin capacitance material can be the same as is used for the 50µm core material. This was verified at the three PCB facilities previously mentioned.

Figure 2. Cross-section of board using 12µm capacitance layer.

4) Through hole and micro-via plating reliability
Figures 2-4 shows the cross-sections of the boards using thin capacitive material. Figure 2 is the cross-section of a PTH in a board using 12µm dielectric thickness capacitor material.

Figure 3. Cross-section of board using 24µm capacitance layer with Microvia.

Figure 3 is of a 24µm capacitor board connected with a micro-via. Because the material is non-woven, it is easily laser ablated and plated.

Figure 4. Cross-section of 24 layer board using 12µm capacitance layer after 6x Solder Shock.

Figure 4 is of a 24 layer board using the 12 micron material after 6x Solder shock at 288°C. Good connection of the plated copper to the thin dielectric layers is observed. Also, all the cross-sections show good compatibility with the surrounding FR-4 laminates.

Electrical performance of the board using thin capacitive material

Figure 5. Board used for the noise current measurement [4].

Many advantages on electrical performance, such as power distribution and Electro Magnetic Interference (EMI), can be expected by using thin capacitive material in PWB.

Conducted emissions on the supply line for a microprocessor (MPU) running at 40MHz were measured by VDE method. No discrete decoupling capacitors were mounted on the four-layer board (See Figure 5).

Figure 6. Comparison of noise current with standard laminate core and 10 µm core [5].

Comparison of conducted emissions between conventional standard 400µm laminate core and 10µm thin film capacitive core are shown in the Figure 6. Significant reduction of emissions in the frequency range of 150 to 550MHz, which is known as the difficult range to reduce by discrete capacitors were observed by the thin film capacitive core. Lower effective inductance and larger capacitance of the thin film core structure improves performance of supply decoupling for MCUs.

The reduction in EMI is a good benefit of using these thin capacitor substrates, but the major benefit is in the reduction in impedance of the power planes.

Figure 7. Test Vehicle for measuring power plane impedance.

Figure 7 shows the test vehicle used to check the power plane impedance.

Figure 8- Self Impedance Results.

Figure 8 shows the reduction in self-impedance of various capacitive layers.

Figure 9. Transfer Impedance Results.

Figure 9 shows the transfer impedance change in capacitance at 1” distance. The distance from the chip and the shape of the planes will impact these numbers, but it is easily seen that the thinner the material the lower the impedance. This is a very important design consideration and shows the benefit of the embedded capacitor material.

Conclusion

Contributions and influences of copper foil and dielectric resin properties to construct a thin dielectric capacitive material have been investigated. Suitable copper foil type and dielectric resin was selected to construct thin film capacitive material. The thin film capacitive materials, 12, 16 and 24 micron dielectric thickness, were capable of processing through the conventional PWB manufacturing steps. This was shown at multiple PCB shop locations.

The electrical performance and capacitance values are improved over the traditional FR4 laminate substrates. The ability to withstand 500 volt Hi-Pot testing (even at 10µm) is significant, and has not been demonstrated by any other thin polymer capacitive substrate. A dramatic reduction in EMI and both self and transfer impedance will allow for better system performance especially at high speeds. This will also help to simplify the designer’s tasks. We are continuing to work on driving the thickness even lower. Work on both the foil and dielectric are needed to make this a reality. Also, we are developing a ceramic loaded substrate for use as a replacement for discrete capacitors on daughter cards and chip packages.

As the demand for a power distribution system with low impedance and control of EMI increases for hi-end computing boards with high signal frequency, the usage of thin film capacitive material in PCBs is expected to grow.

Acknowledgement

The authors would like to acknowledge our colleagues at Mitsui Mining & Smelting Co. LTD and Oak-Mitsui for their work for preparing and evaluating the material. We appreciate Atsushi Nakamura and his team of Hitachi LTD for providing data and suggestions. We appreciate the manufacturing of the test vehicles for impedance testing by Howard Jones of Sanmina-SCI in Owego, NY.